An electrostatic discharge (ESD) protection device including: a substrate including: a first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region has a first conductivity type and a first doping concentration and the first and third doped regions have a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; and a doped island region disposed within the second doped region, the first and second doped terminal regions and doped island region have the second conductivity type and a third doping concentration, the third doping concentration higher than the first and second doping concentrations; and conductive terminals respectively coupled to the doped terminal regions; and an insulation layer arranged on the substrate between the conductive terminals and covering at least the second doped region.

A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.

A semiconductor device is disclosed including, among other things, a first device region defined above a substrate, wherein the first device region is isolated from the substrate by a buried insulating layer, the first device region including a first power rail, a first signal line traversing at least a first portion of the first device region, and a first plurality of edge cells positioned in the substrate adjacent the first device region, wherein at least a first edge cell of the first plurality of edge cells includes a substrate contact connecting the first power rail to the substrate and a first signal line antenna diode connecting the first signal line to the substrate.

A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.

The present disclosure provides a silicon-controlled rectifier structure and a manufacturing method therefor. The silicon-controlled rectifier structure comprises a substrate; and an N-Well and a P-Well in the substrate, wherein an N-type heavily-doped region 410 and a P-type heavily-doped region 422 which are connected to an anode are provided in the N-Well, and a floating guard ring 416 is further provided in the N-Well between the N-type heavily-doped region 410 and the P-type heavily-doped region 422, the guard ring being spaced from the N-type heavily-doped region 410 by a shallow trench isolation, and an active area having a predetermined width exists between the guard ring and the P-type heavily-doped region 422; and an N-type heavily-doped region 414 and a P-type heavily-doped region 424 which are connected to a cathode are provided in the P-Well.

A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.

According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.

The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N.sup. drift layer. A concentration slope , which is derived from displacements in a depth TB (m) and an impurity concentration CB (cm.sup.3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.030.7}.

A method for fabricating a protection device includes forming a doped well with a first-type impurity in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.