A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.

A semiconductor element capable of adjusting a barrier height .sub.Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the change of the barrier height caused by the bias described above up to a deep degeneration range. An electron Fermi level (E.sub.F) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

In one embodiment, an overvoltage protection device may include a semiconductor substrate comprising an n-type body region. The overvoltage protection device may further include a first p-type region disposed in a first surface region of the semiconductor substrate, and forming a first P/N junction with the n-type body region, and a second p-type region disposed in a second surface region of the semiconductor substrate opposite the first surface, and forming a second P/N junction with the n-type body region, wherein the n-type body region, first p-type region, and second p-type region form a breakdown device having a breakdown voltage greater than 100V when an external voltage is applied between the first surface region and second surface region.

A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region.

A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface. The semiconductor structure also includes a first diffusion layer disposed in the substrate and adjacent to the first surface, and a first electrode layer disposed on the first diffusion layer. The semiconductor structure further includes a second diffusion layer disposed in the substrate and adjacent to the second surface, and a plurality of diffusion regions disposed in the second diffusion layer. The semiconductor structure further includes a second electrode layer disposed on the second diffusion layer and in contact with the plurality of diffusion regions. The second diffusion layer is coupled to the plurality of diffusion regions through the second electrode layer. The substrate is sandwiched between the first electrode layer and the second electrode layer.

A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with <100> orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with <100> orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary. Next is annealing the respective first and second cleaned wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers, followed by bonding together respective first and second heat-treated wafers to yield a mated and/or bonded four-layer substrate having a first heavy doped n-type layer, a second gradient doped n-type layer, a third gradient doped p-type layer, and a fourth heavy doped p-type layer.

A method for fabricating a protection device includes forming a doped well with a first-type impurity in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.

The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N.sup. drift layer. A concentration slope , which is derived from displacements in a depth TB (m) and an impurity concentration CB (cm.sup.3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.030.7}.

The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N.sup. drift layer. A concentration slope , which is derived from displacements in a depth TB (m) and an impurity concentration CB (cm.sup.3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.030.7}.

A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.