A method comprises providing a substrate comprising an n-type Al/In/GaN semiconductor material. A surface of the substrate is dry-etched to form a trench therein and cause dry-etch damage to remain on the surface. The surface of the substrate is immersed in an electrolyte solution and illuminated with above bandgap light having a wavelength that generates electron-hole pairs in the n-type Al/In/GaN semiconductor material, thereby photoelectrochemically etching the surface to remove at least a portion of the dry-etch damage.

A stacked high-blocking III-V power semiconductor diode, with a p+ or n+ substrate layer, a p− layer, an n− region with a layer thickness of 10 μm-150 μm, and an n+ or p+ layer, wherein all layers comprise a GaAs compound, a first metallic contact layer and a second metallic contact layer and a hard mask layer with at least one seed opening, wherein the hard mask layer is integrally bonded to the substrate layer or integrally bonded to the p− layer, the n− region extends within the seed opening and over an edge region, adjacent to the seed opening, of a top side of the hard mask layer and the n− region within the seed opening is integrally bonded to the p− layer or to the n+ substrate layer and in the edge region of the top side of the hard mask layer to the hard mask layer.

A semiconductor structure having: a crystalline substrate; a single crystalline semiconductor layer grown on the substrate; and a heat generating semiconductor device formed on a portion of the single crystalline layer. The substrate has an aperture in a selected portion thereof disposed in regions in the semiconductor layer under the heat generating device the aperture extending from a bottom portion of the substrate to the single crystalline semiconductor layer. Single crystalline or polycrystalline, thermal conductive material is disposed in the aperture, such material filling the aperture and extending from the bottom of the substrate, to and in direct contact with, the semiconductor layer.

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

A semiconductor device structure may include a semiconductor device, disposed at least in part in a semiconductor substrate, and a first insulator layer, disposed on a surface of the semiconductor device, and comprising a first contact aperture, disposed within the first insulator layer. The semiconductor device structure may also include a first contact layer, comprising a first electrically conductive material, disposed over the insulator layer, and being in electrical contact with the semiconductor device through the first contact aperture, and a second insulator layer, disposed over the first contact layer, wherein the second insulator layer further includes a second contact aperture, displaced laterally from the first contact aperture, by a first distance. The semiconductor device structure may further include a second contact layer, comprising a second electrically conductive material, disposed over the second insulator layer, and electrically connected to the semiconductor device through the first and second contact aperture.

A stacked high-blocking III-V semiconductor power diode and manufacturing method, wherein the III-V semiconductor power diode comprises a first highly doped semiconductor contact area, a low-doped semiconductor drift region disposed beneath the first semiconductor contact area, a highly doped second semiconductor contact area disposed beneath the semiconductor drift region, and two terminal contact layers, at least the first semiconductor contact area forms a core stack, the core stack is surrounded by a dielectric frame region along the side face, the upper surface or lower surface of the core stack and the dielectric frame region terminate with each other or form a step with respect to each other, and semiconductor areas of the III-V semiconductor power diode arranged beneath the first semiconductor contact area are each either surrounded by the core stack or form a carrier portion.

A stacked III-V semiconductor photonic device having a second metallic terminal contact layer at least formed in regions, a highly doped first semiconductor contact region of a first conductivity type, a very low doped absorption region of the first or second conductivity type having a layer thickness of 20 μm-2000 μm, a first metallic terminal contact layer, wherein the first semiconductor contact region extends into the absorption region in a trough shape, the second metallic terminal contact layer is integrally bonded to the first semiconductor contact region and the first metallic terminal contact layer is arranged below the absorption region. In addition, the stacked III-V semiconductor photonic device has a doped III-V semiconductor passivation layer of the first or second conductivity type, wherein the III-V semiconductor passivation layer is arranged at a first distance of at least 10 μm to the first semiconductor contact region.

Methods are provided of selectively obtaining n-type and p-type regions from the same III-Nitride layer deposited on a substrate without using diffusion or ion-implantation techniques. The III-Nitride layer is co-doped simultaneously with n-type and p-type dopants, with p-type dopant concentration higher than n-type dopant to generate p-n junctions. The methods rely on obtaining activated p-type dopants only in selected regions to generate p-type layers, whereas the rest of the regions effectively behave as an n-type layer by having deactivated p-type dopant atoms.

A lateral superjunction includes a substrate layer, a selective epitaxy layer deposited on the substrate layer, a trench formed into the selective epitaxy layer to expose a portion of the substrate layer, a first layer of semiconductor deposited in the trench, a second layer of semiconductor deposited adjacent to the first layer, and a first end layer of semiconductor deposited adjacent to the first layer of semiconductor and a second end layer of semiconductor deposited adjacent to the second layer of semiconductor.