The present invention provides a method for producing a semiconductor device, which can evaluate the p-GaN crystal quality of the wafer for actually forming devices thereon. The method for producing a semiconductor device having a p-type GaN layer comprises forming a p-type layer on a wafer through MOCVD; measuring the PL spectrum of the p-type layer; and selecting wafers where the intensity ratio of the emission intensity in the blue band of 430 nm to 450 nm to the band edge emission intensity of the PL spectrum is not larger than 0.5. Thus, a semiconductor device exhibiting reduced contact resistance or leakage current can be produced.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

A P-i-N diode structure includes a group III-N semiconductor material disposed on a substrate. An n-doped raised drain structure is disposed on the group III-N semiconductor material. An intrinsic group III-N semiconductor material is disposed on the n-doped raised drain structure. A p-doped group III-N semiconductor material is disposed on the intrinsic group III-N semiconductor material. A first electrode is connected to the p-doped group III-N semiconductor material. A second electrode is electrically coupled to the n-doped raised drain structure. In an embodiment, a group III-N transistor is electrically coupled to the P-i-N diode. In an embodiment, a group III-N transistor is electrically isolated from the P-i-N diode. In an embodiment, a gate electrode and an n-doped raised drain structure are electrically coupled to the n-doped raised drain structure and the second electrode of the P-i-N diode to form the group III-N transistor.

A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15 and 0.65. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.

A method for producing a vertical component comprising with the basis of a III-N material, comprising providing platelets made of the III-N material obtained by epitaxy on pads, the platelets comprise at least first and second layers doped and stacked on one another in a vertical direction. The method further includes the production of a first electrode and the production of a second electrode located on the platelet and configured such that a current passing from one electrode to the other passes through at least the second layer in all of its thickness, the thickness being taken in the vertical direction.

A method and stacked semiconductor device having a top surface, a bottom surface, and at least one side surface that connects the top surface with the bottom surface. The bottom surface is formed of a substrate layer or a rear side contact layer arranged below the substrate layer. On the substrate layer, a first semiconductor layer of a first conductivity type is arranged and on the first semiconductor layer at least one second semiconductor layer of a second conductivity type is arranged. The first and second semiconductor layers are formed of a III-V material or consist of a III-V material. The first and second conductivity types are different. The top surface is at least partially formed by a passivation layer. Along the side surface, an amorphized and/or insulating region extending to a depth is formed, and the depth is perpendicular or substantially perpendicular to the layer stack.

There is provided a semiconductor device, including: a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode electrically connected to the first semiconductor layer on a lower surface of the first semiconductor layer, wherein the insulating film is constituted including a first insulating layer and a second insulating layer, the first insulating layer is disposed so as to cover a corner portion where the side surface of the mesa structure and the outside upper surface of the mesa structure are connected to each other, the second insulating layer is disposed so as to cover the pn junction interface exposed on the side surface of the mesa structure, or is disposed to constitute an entire thickness of the insulating film directly under the electrode end of the first electrode so as to cover the area directly under the electrode end, the relative dielectric constant of the second insulating layer is equal to or larger than the relative dielectric constant of the semiconductor member, and the relative dielectric constant of the first insulating layer is smaller than the relative dielectric constant of the second insulating layer.

A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15? and 0.65?. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.