A lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.

A bipolar junction transistor having a relatively reduced size and an improved current gain and a method of manufacturing the same are disclosed. The bipolar junction transistor includes a plurality of emitter regions disposed in a substrate, a plurality of base regions disposed in the substrate and configured to surround the emitter regions, respectively, and a collector region disposed in the substrate and configured to surround the base regions. The plurality of emitter and base regions may be arranged in a matrix.

A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer; etching the first base layer; forming a second base layer on the intrinsic base semiconductor layer adjacent the first base layer; removing the first mask; applying a second mask to the base layers; simultaneously etching the layers to produce extrinsic bases of reduced cross dimensions; disposing spacers on the extrinsic bases; etching around the bases leaving the intrinsic base semiconductor layer under the bases and spacers; implanting ions into sides of the intrinsic base semiconductor layer under the first extrinsic base to form a first emitter/collector junction and into sides of the intrinsic base semiconductor layer under the second extrinsic base to form a second emitter/collector junction; depositing semiconductor material adjacent to the junctions and the trenches; and removing the applied second mask.

Integrated circuits with lateral bipolar transistors and methods for fabricating the same are provided. An exemplary integrated circuit includes a semiconductor layer overlying an insulator layer. The semiconductor layer includes a first region having a first thickness and a trench region having a second thickness less than the first thickness. The integrated circuit further includes an isolation region formed over the trench region of the semiconductor layer. Also, the integrated circuit includes a lateral bipolar transistor including a base formed in the trench region of the semiconductor layer, an emitter, and a collector.

A semiconductor integrated circuit device may include a semiconductor substrate, an active well, an emitter, a base, a collector, a body contact region, and a blocking well. The semiconductor substrate may have a first conductive type. The active well may be formed in the semiconductor substrate. The active well may have a second conductive type. The emitter and the base may be formed in the active well. The collector may be formed in the semiconductor substrate outside the active well. The body contact region may be formed in the semiconductor substrate to electrically connect the collector with the semiconductor substrate. The body contact region may have a conductive type substantially the same as that of the collector. The blocking well may be configured to surround an outer wall of the body contact region. The blocking well may have the second conductive type.

A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.

A method and a system for developing semiconductor device fabrication processes are provided. The developments of vertical and lateral semiconductor device fabrication processes can be integrated in the system. First, according to a target semiconductor device and a specification thereof, an initial target model and a general database are captured. The initial target model and the general database are compared to obtain a corresponding relationship. According to the corresponding relationship, multiple fixed fabrication parameters of the general database are applied to the initial target model, such that at least one adjustable parameter is defined. Thereafter, the parameter is set according to a setting instruction received through a user interface to produce a target model to be simulated. A simulation test is performed with the target model, and the adjustable parameter is modified until the simulation result of the target model satisfies a standard result.

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer on a semiconductor substrate, a second terminal having a second raised semiconductor layer on the semiconductor substrate, and an intrinsic base on the semiconductor substrate. The intrinsic base is positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The intrinsic base includes a portion containing silicon-germanium with a germanium concentration that is graded in the lateral direction.

Disclosed are a forksheet semiconductor structure and a method of forming the structure. The structure can include a dielectric body with a first sidewall and a second sidewall opposite the first sidewall. The structure can include a first transistor, which incorporates first semiconductor nanosheet(s) positioned laterally immediately adjacent to the first sidewall of the dielectric body, and a second transistor, which incorporates second semiconductor nanosheet(s) positioned laterally immediately adjacent to the second sidewall. The first transistor and the second transistor can both be bipolar junction transistors (BJTs) (e.g., PNP-type BJTs, NPN-type BJTs or a PNP-type BJT and an NPN-type BJT). Alternatively, the first transistor can be a BJT (e.g., a PNP-type BJT or an NPN-type BJT) and the second transistor can be a field effect transistor (FET) (e.g., an N-type FET (NFET) or a P-type FET (PFET)).