An integrated circuit includes a semiconductor substrate having a doped region, e.g. a DWELL, with a first conductivity type. A source region is located within the doped region, the source region having a second opposite conductivity type. A drain region having the second conductivity type is spaced apart from the source region. A gate electrode is located between the source region and the drain region, the gate electrode partially overlapping the doped region. A body region having the first conductivity type is located within the doped region. A dielectric layer forms a closed path around the body region.

An insulated gate bipolar transistor (IGBT) structure including a substrate and a first gated PNPN diode is provided. The first gated PNPN diode is located on the substrate. The first gated PNPN diode includes a first gate, a first source/drain extension (SDE) region, and a second SDE region. The first gate is located on the substrate. The first SDE region and the second SDE region are located in the substrate on two sides of the first gate.

The present invention relates to an insulated gate bipolar transistor (IGBT) and, more particularly, to an insulated gate bipolar transistor that has multiple mesas having different widths, configured to promote the buildup and accumulation of hole carriers, thereby facilitating relatively easy subsequent processing, while maximizing conductivity modulation.

A method for manufacturing an IGBT device includes: forming a cell structure of the IGBT device in a substrate; forming front metal layers on the substrate; thinning the substrate; forming a collector region on the back of the substrate; forming back metal layers on the back of the substrate; and forming target metal on the front and back of the substrate via electroless plating processes.

A semiconductor device includes a substrate, an epitaxial layer, an emitter region, and a collector region. The epitaxial layer is disposed over the substrate and has a first conductivity type. The drift region is disposed in the epitaxial layer and has a second conductivity type that is the opposite of the first conductivity type. The emitter region is disposed in the epitaxial layer outside the drift region. The collector region is disposed in the drift region. The semiconductor device also includes a doped region. The doped region is disposed adjacent to the bottom surface of the drift region and has the first conductivity type.

A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip. Therefore, effects of low power consumption, a reduced size, and high speed of a chip may be achieved.

A semiconductor device includes: a semiconductor substrate; a plurality of trenches provided on a top surface side of the semiconductor substrate; am insulated gate electrode structure buried inside the respective trenches; an interlayer insulating film deposited on top surfaces of the semiconductor substrate and the insulated gate electrode structure; and a silicide layer deposited at a bottom of a contact hole penetrating the interlayer insulating film so as to be in contact with the top surface of the semiconductor substrate interposed between the trenches adjacent to each other, wherein at least a part of a bottom surface of the silicide layer is located at a higher position than a bottom surface of the interlayer insulating film.

An insulated gate bipolar transistor (IGBT) structure including a substrate and a first gated PNPN diode is provided. The first gated PNPN diode is located on the substrate. The first gated PNPN diode includes a first gate, a first source/drain extension (SDE) region, and a second SDE region. The first gate is located on the substrate. The first SDE region and the second SDE region are located in the substrate on two sides of the first gate.

A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.

A method of forming a semiconductor device and the structure of the semiconductor device are provided. The manufacturing method includes the following steps of: providing a semiconductor substrate with a front side and a back side; forming a collector layer in the back side; conducting a first Hydrogen implant process to the back side to form an N-type region and baking the N-type region with a first annealing temperature to form a field stop buffer layer; conducting a second Hydrogen implant process to the back side to form a lifetime control site and baking the lifetime control site with a second annealing temperature to form a defect layer, wherein the second annealing temperature being lower than the first annealing temperature; and forming a metal layer on the back side.