A semiconductor apparatus including first, second, and third silicon layers, the first silicon being coupled to the second silicon layer and the second silicon layer being coupled to the third silicon layer. The apparatus includes a trench formed in the first silicon layer and in at least a portion of the second silicon layer, an isolation region formed in at least the second silicon layer, where the isolation region extends from the trench to the third silicon layer. The apparatus also includes a first main terminal one and a first gate terminal coupled to a first portion of the first silicon layer, a second main terminal one and a second gate terminal coupled to a second portion of the first silicon layer, a main terminal two coupled to the third silicon layer, and one or more silicon regions in the first silicon layer and in the third silicon layer.

A TRIAC semiconductor includes an N? region, multiple N+ regions, and a trench. The N? region is sandwiched between two P regions. The first P region is connected to an MT2 terminal and the second P region is connected to two MT1 terminals. The multiple N+ regions are located within the first P region. The trench is located between two gate terminals.

A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.

A one-way switch has a gate referenced to a main back side electrode. An N-type substrate includes a P-type anode layer covering a back side and a surrounding P-type wall. First and second P-type wells are formed on the front side of the N-type substrate. An N-type cathode region is located in the first P-type well. An N-type gate region is located in the second P-type well. A gate metallization covers both the N-type gate region and a portion of the second P-type well. The second P-type well is separated from the P-type wall by the N-type substrate except at a location of a P-type strip that is formed in the N-type substrate and connects a portion on one side of the second P-type well to an upper portion of said P-type wall.

The present disclosure concerns a method of forming an electronic power component inside and on top of a semiconductor substrate, comprising the following successive steps: a) forming of a peripheral groove in the semiconductor substrate on the side of a first surface of the semiconductor substrate; b) deposition of an oxygen-doped polysilicon layer, on top of and in contact with the bottom and the lateral walls of the peripheral groove and with the first surface of the semiconductor substrate; c) local deposition of a glass layer, on the oxygen-doped polysilicon layer, the glass layer extending in the peripheral groove and further extending over a portion of the first surface of the semiconductor substrate; and d) etching of the oxygen-doped polysilicon layer so that it extends on the first surface of the semiconductor substrate beyond the glass layer.

A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.

A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.

A semiconductor device includes a semiconductor substrate having a first surface and a second surface, first to eighth regions, a first thyristor, and a second thyristor. The seventh region with the impurity concentration higher than that of the first region is formed in the first region while being apart from the sixth region electrically connected to the gate electrode, and being electrically connected to the first electrode. The eighth region with the impurity concentration higher than that of the third region is formed in contact with the second surface side of the third region and the fourth region, and with the second surface, while being electrically connected to the fourth region by the second electrode. The seventh region has the impurity concentration higher than that of the first region. The eighth region has the impurity concentration higher than that of the third region.

The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the B-TRAN type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.