A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of .sup.18O greater than 10 percent.

Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. A layer stack is formed on a semiconductor substrate comprised of a single-crystal semiconductor material. The layer stack includes a semiconductor layer comprised of a III-V compound semiconductor material. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer extends laterally beneath the layer stack.

In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

A semiconductor device includes a first semiconductor structure. The first semiconductor structure includes a first semiconductor material having a band-gap. The first semiconductor structure has a first surface. An insulating layer has first and second opposing surfaces. The first surface of the insulating layer is on the first surface of the first semiconductor structure. A second semiconductor structure is on the second surface of the insulating layer and includes a second semiconductor material having a band-gap that is smaller than the band-gap of the first semiconductor material. A floating electrode couples the first semiconductor structure to the second semiconductor structure.

Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase V.sub.t. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease V.sub.t. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies V.sub.t. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.

Flexible transistors and electronic circuits incorporating the transistors are provided. The flexible transistors promote heat dissipation from the active regions of the transistors while preserving their mechanical flexibility and high-frequency performance. The transistor designs utilize thru-substrate vias (TSVs) beneath the active regions of thin-film type transistors on thin flexible substrates. To promote rapid heat dissipation, the TSVs are coated with a material having a high thermal conductivity that transfers heat from the active region of the transistor to a large-area ground.

Provided are a semiconductor structure and manufacturing method thereof, the semiconductor comprising: a base (10), wherein the base (10) comprises strip trenches (101) arranged parallelly; and a heterojunction structure (11) located on bottom walls and sidewalls of the strip trenches and on the base other than the strip trenches, wherein regions of the heterojunction structure located on the bottom walls and on the base other than the strip trenches are polarized regions, regions of the heterojunction structure on the sidewalls are non-polarized regions, and the polarized regions contain carriers; the heterojunction structure comprises a source region (11a) and a drain region (11b) respectively located at both ends of each of the strip trenches, and a gate region (11c) between the source region and the drain region; and the carriers between the source region and the drain region are confined to flow in each of the polarized regions.

An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.