Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding position of the source region and a corresponding position of the drain region. The gate structure includes a conductive layer having an inclined side surface facing toward the conductive plug. Compared with a traditional gate structure, in the solutions of the present disclosure, a distance between the conductive layer having the inclined side surface and the conductive plug is increased, thereby reducing a parasitic capacitance between the gate structure and the conductive plug, such that capacitance between a gate and the source/drain region is reduced, and device characteristics are improved.

Provided is a semiconductor device including a semiconductor substrate having a transistor portion and a diode portion; and an emitter electrode and a gate electrode provided above a front surface of the semiconductor substrate, wherein the transistor portion has a plurality of trench portions electrically connected to the gate electrode, a drift region of a first conductivity type provided in the semiconductor substrate, a base region of a second conductivity type provided above the drift region, and a trench bottom barrier region of a second conductivity type provided between the drift region and the base region and having a higher doping concentration than that of the base region, and the trench bottom barrier region is electrically connected to the emitter electrode.

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

A method for fabricating a semiconductor transistor is disclosed. A substrate of a first conductivity type is provided. An ion well of a second conductivity type is formed in the substrate. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate. A gate dielectric layer is formed on the epitaxial channel layer. A gate is formed on the gate dielectric layer. A source region and a drain region are then formed in the substrate. The source region and the drain region have the first conductivity type.

A display device provided with an image capturing function is provided. A display device with both high viewing angle characteristics and high image capturing performance is provided. The display device includes a light-emitting and light-receiving element and a color filter. The light-emitting and light-receiving element includes a light-emitting and light-receiving region having a function of emitting light of the first color and a function of receiving light of the second color. The color filter is positioned over the light-emitting and light-receiving element and has a function of transmitting the light of the first color and a function of blocking the light of the second color. The color filter includes an opening portion. The light-emitting and light-receiving region includes a portion positioned in the inside of the opening portion in the plan view.

A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A semiconductor device includes a semiconductor substrate and a metal film. The metal film is located on the semiconductor substrate. The metal film includes a portion to have a Schottky junction with the semiconductor substrate. The metal film is made of an aluminum alloy in which an element is added to aluminum. The metal film includes a lower metal layer and an upper metal layer. The lower metal layer is located on the semiconductor substrate. The upper metal layer stacks on the lower metal layer. The lower metal layer has a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer.

A novel semiconductor device is provided. A memory string extends in a Z direction. The memory string achieves high-speed operation by using an oxide semiconductor for a semiconductor layer. The memory string includes a MONOS memory cell. A tunnel layer is provided on a control gate side, and a block layer is provided on a semiconductor side. During erase operation, a hole is injected into a charge accumulation layer from the control gate side.

A novel metal oxide and a formation method thereof are provided. The metal oxide includes a first crystal, a second crystal, and a region positioned between the first crystal and the second crystal. The c-axis of the first crystal is substantially parallel to the c-axis of the second crystal. The crystallinity of the region is lower than those of the first crystal and the second crystal. The width of the region in the direction perpendicular to the c-axis of the first crystal is greater than 0 nm and less than 1.5 nm. The first crystal and the second crystal each have a layered crystal structure.