Semiconductor structures are disclosed which comprise semiconductor devices having thin multi-layer channel stacks. In one example, a semiconductor structure comprises a gate structure comprising a multi-layer channel stack. The multi-layer channel stack comprises a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first and second dielectric layers. The semiconductor structure further comprises a first source/drain region disposed on a first side of the gate structure and in electrical contact with a first end portion of the multi-layer channel stack and a second source/drain region disposed on a second side of the gate structure and in electrical contact with a second end portion of the multi-layer channel stack.

This disclosure provides a display device, an array substrate, a thin film transistor and a fabrication method thereof. The thin film transistor includes an active layer, a gate insulating layer, a gate electrode, a dielectric layer, a source electrode and a drain electrode. The active layer has a channel region, doped regions at both sides of the channel region, and buffer regions each of which arranged between the corresponding doped region and the channel region, and a doping concentration of the buffer regions is less than that of the doped regions. The gate insulating layer is at a side of the active layer, covers the channel region and the buffer regions, and exposes the doped regions. The gate electrode is on a surface of the gate insulating layer facing away from the active layer.

An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Provided is a semiconductor device, wherein the buffer region of the semiconductor substrate has a plurality of hydrogen chemical concentration peaks arranged in different positions in the depth direction of the semiconductor substrate, a plurality of doping concentration peaks; and a high concentration region provided between the deepest hydrogen chemical concentration peak and the drift region, wherein the doping concentration distribution of the depth direction of the high concentration region has a slope where the doping concentration gradually decreases toward the drift region, wherein the slope includes a convex portion on top, wherein in an approximate concentration line that approximates a gradient of the slope with a straight line, when the concentration in a depth position of the shallowest doping concentration peak is referred to as the shallowest reference concentration, the doping concentration of the shallowest doping concentration peak is from 5% to 50% of the shallowest reference concentration.

According to one embodiment, a display device comprises an insulating base, a light-emitting element, a pixel circuit including a first transistor, and a first shield that shields a part of the pixel circuit from light. The first transistor includes a first semiconductor layer, and a first gate electrode between the insulating base and the first semiconductor layer. The first shield is disposed between the insulating base and the first gate electrode in the thickness direction and overlaps a channel region where the first semiconductor layer and the first gate electrode intersect.

A thin-film transistor element including a gate layer, an oxide semiconductor thin-film, a gate insulating film disposed between the gate layer and the oxide semiconductor thin-film, a pair of source-drain electrodes electrically connected to the oxide semiconductor thin-film, and a resin film covering the oxide semiconductor thin-film is provided. The oxide semiconductor thin-film contains two or more metal elements selected from indium, gallium, zinc, and tin. The resin film is in contact with the oxide semiconductor thin-film. The resin film may include a compound that contains a SiH group. The resin film may be formed by applying a composition including a SiH group-containing compound onto the oxide semiconductor thin-film, and heating the composition.

A method for manufacturing a semiconductor device with a high yield is provided. In a semiconductor device including an oxide semiconductor over a substrate, when an insulator in contact with the oxide semiconductor, such as a gate insulator or an interlayer film, is deposited, the insulator can be deposited without diffusion of hydrogen into the oxide semiconductor by setting a constant derived from deposition conditions within a given range. Specifically, setting values of deposition power, the effective electrode area, deposition pressure, and the flow rate of a deposition gas containing hydrogen in the deposition conditions can be selected as appropriate.

A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the LDMOS device are disclosed. The device includes: a substrate (101) having a second conductivity type; a drift region (102) that has a first conductivity type and is disposed on the substrate (101), wherein the first conductivity type is opposite to the second conductivity type; a plurality of layers of doped structures disposed in the drift region (102), each layer of the doped structure comprising at least one doped bar (105) extending in a lengthwise direction of a conductive channel; and a plurality of doped polysilicon pillars (106) disposed in the drift region (102) so as to extend downward through the doped bar (105) of at least one of the layer of doped structures, wherein ions doped in the doped polysilicon pillars (106) and ions doped in the doped bar have opposite conductivity types.

A preparation method for semiconductor device, comprising: forming a body region (110) in the drift region (100), forming a first doped region (111) and a second doped region (112) in the body region (110); forming a first trench (171) penetrating the first doped region (111) and the body region (110) and extending to the drift region (100); forming an extension region (150) with a conductivity type opposite to that of the drift region (100) and surrounding the bottom wall of the first trench (171); filling the first trench (171) with a dielectric layer (130) formed on the sidewall of the trench, a first conductive structure (141) located at the bottom of the trench and a second conductive structure (142) located at the top of the trench; forming a second trench (172) penetrating the body region (110) and extending into the drift region (100); filling the second trench (172) with a third conductive structure (143) and a dielectric layer (130) formed on the inner wall of the trench. The second conductive structure (142) is electrically connected with the gate, and the first doped region (111), the second doped region (112), and the third conductive structure (143) are electrically connected with the first electrode (130).

A semiconductor device includes a barrier layer, a channel layer, a regrowth layer, a vacancy generation region, and a source electrode or a drain electrode. The barrier layer includes a first nitride semiconductor. The channel layer includes a second nitride semiconductor and is bonded to the barrier layer at a first surface. The regrowth layer includes an n-type nitride semiconductor and is provided in a region dug deeper than an interface between the barrier layer and the channel layer from a second surface of the barrier layer. The second surface is on opposite side to the first surface. The vacancy generation region includes a nitrogen-capturing element and is provided in a region of the regrowth layer shallower than the interface between the barrier layer and the channel layer. The source electrode or the drain electrode is provided on the regrowth layer.