An oxide crystal includes an oxide having a rutile-type structure. The oxide crystal is oriented to a crystallographic axis direction perpendicular to or parallel to a c-axis, and an atomic ratio of germanium in a metal element in the oxide crystal is greater than 0.5. A crystalline oxide film contains an oxide of germanium. A crystalline multilayer structure includes a crystal substrate, and a crystalline oxide film layered on the crystal substrate. The crystal substrate has a tetragonal crystal structure, and an atomic ratio of germanium in a metal element in the crystalline oxide film is greater than 0.5. A manufacturing method includes atomizing or forming droplets of a raw material solution containing germanium, supplying a carrier gas to the atomized droplets, and carrying the atomized droplets onto a crystal substrate having a tetragonal crystal structure and simultaneously causing the atomized droplets to thermally react on the crystal substrate.

This nitride semiconductor device is provided with: a depletion type transistor which comprises a first gate terminal, a first source terminal and a first drain terminal; and an enhancement type transistor which comprises a second gate terminal, a second source terminal and a second drain terminal. The second drain terminal is connected to the first source terminal; and the second source terminal is connected to the first gate terminal. The depletion type transistor comprises: an electron transit layer which is configured from a nitride semiconductor that contains aluminum in the crystal composition; and an electron supply layer which is formed on the electron transit layer and is configured from a nitride semiconductor that contains a larger amount of aluminum in the composition than the electron transit layer.

A semiconductor device, the semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; and a via disposed through the second level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

A 3D semiconductor device including: a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; and a third die, comprising a third die area and a plurality of second bottom contacts, wherein said first die area is greater than the sum of said second die area and said third die area, wherein said second die and said third die are both placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, and wherein said plurality of second bottom contacts are connected to said first die top contacts.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A semiconductor device according to an embodiment of the present disclosure includes a channel layer and a barrier layer in this order on a substrate. The semiconductor device further includes a gate electrode, a source electrode, and a drain electrode that are formed on the substrate via the channel layer and the barrier layer. The gate electrode, the source electrode, and the drain electrode extend in a first direction. The channel layer or the barrier layer has a plurality of non-conductive regions formed at positions opposed to the gate electrode and arranged side by side, with a predetermined interval interposed therebetween, in an extending direction of the gate electrode. The non-conductive regions inhibit a current from flowing to the channel layer.

A semiconductor device according to the present disclosure includes a SiC substrate, an AlN nucleation layer provided on the SiC substrate, an AlGaN buffer layer provided on the AlN nucleation layer, a GaN channel layer provided on the AlGaN buffer layer, an AlGaN barrier layer provided on the GaN channel layer and a drain electrode, a source electrode, and a gate electrode each provided above the AlGaN barrier layer, wherein the AlGaN buffer layer has an Al composition ratio decreasing from the SiC substrate toward the GaN channel layer, and a thickness of the AlN nucleation layer is less than or equal to 30 nm.

A heterojunction bipolar transistor includes a collector layer, a base layer, an emitter layer, and a ballast resistance layer. The collector layer is made of an n-type compound semiconductor material. The base layer is disposed on the collector layer and is made of a p-type compound semiconductor material. The emitter layer is disposed on the base layer and is made of an n-type compound semiconductor material having a band gap larger than a band gap of the base layer. The ballast resistance layer is disposed on the emitter layer and is made of an intrinsic or p-type compound semiconductor material.

According to one embodiment, a semiconductor device include first to third electrode, a semiconductor member, a first conductive member, and a first insulating member. A second insulating region of the first insulating member includes a first face facing the third partial region of the first semiconductor region. The third insulating region of the first insulating member includes a second face facing the third partial region of the first semiconductor region. The first face includes a first end on a side of the first electrode in the first direction. The second face includes a second end on a side of the second electrode in the first direction. A second position of the second end in the second direction is different from a first position of the first end in the second direction.

A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.