A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

A semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and an insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode, the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode, a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.

A semiconductor device structure includes a region of semiconductor material comprising a first conductivity type, an active region, and a termination region. A first active trench structure is disposed in the active region, and a second active trench structure is disposed in the active region and laterally separated from the first active trench by an active mesa region having a first width. A first termination trench structure is disposed in the termination region and separated from the second active trench by a transition mesa region having a second width and a higher carrier charge than that of the active mesa region. In one example, the second width is greater than the first width to provide the higher carrier charge. In another example, the dopant concentration in the transition mesa region is higher than that in the active mesa region to provide the higher carrier charge. The semiconductor device structure exhibits improved device ruggedness including, for example, improve unclamped inductive switching (UIS) performance.

A semiconductor device using a gallium nitride layer has an amorphous glass substrate, an oriented insulating layer arranged on the amorphous glass substrate and having a crystal orientation, a first gallium nitride layer arranged on the oriented insulating layer and in contact with the oriented insulating layer, the first gallium nitride layer being a first conductivity type, a gate electrode opposed to the first gallium nitride layer, and a gate insulating layer between the first gallium nitride layer and the gate electrode. The oriented insulating layer may have a plane with 6-fold rotational symmetry.

Provided is an oxide semiconductor including an oxide of germanium, the oxide semiconductor having a carrier density of 1.0?10.sup.18/cm.sup.3 or more. Provided is method of manufacturing an oxide semiconductor including an oxide of germanium doped on a base, the method including: atomizing or forming droplets of a raw material solution containing a dopant element and germanium, a content of the germanium being greater than a content of the dopant element; supplying a carrier gas to the atomized droplets obtained; and carrying the atomized droplets onto the base by the carrier gas, and simultaneously causing the atomized droplets to thermally react on the base.

A semiconductor device having high operational reliability is provided. This semiconductor device includes a channel layer, a barrier layer, and a first spacer layer provided between the channel layer and the barrier layer, and a second spacer layer provided between the first spacer layer and the barrier layer. The channel layer includes a first nitride semiconductor having a first band gap. The barrier layer includes a second nitride semiconductor having a second band gap larger than the first band gap of the first nitride semiconductor. The first spacer layer includes Al.sub.x1In.sub.y1Ga.sub.(1-x1-y1)N (0<x1?1, 0? y1<1, 0?x1+y1?1). The second spacer layer includes Al.sub.x2In.sub.y2Ga.sub.(1-x2-y2)N (0<x2<x1?1, 0?y2<1, 0<x2+y2<1).

A field effect transistor includes a first etching stop structure and a second etching stop structure. The first etching stop structure is formed on a first side surface of a recess region that is a boundary between a cap layer on a side of a source electrode and the recess region. The second etching stop structure is formed on a second side surface of the recess region that is a boundary between the cap layer on a side of a drain electrode and the recess region.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A field-effect transistor includes a channel layer made of a compound semiconductor and formed on a substrate; a gate electrode formed on the channel layer; and a source electrode and a drain electrode, which are formed with the gate electrode interposed therebetween. At least one of the source electrode and the drain electrode is formed on a substrate side of the channel layer.

A semiconductor device includes: a substrate; a buffer layer; an intermediate layer; an electron transport layer; an electron supply layer; a source electrode and a drain electrode; and a gate electrode. The intermediate layer includes a stack resulting from stacking a first intermediate layer and a second intermediate layer. The second intermediate layer is provided above the first intermediate layer. A first position that is 100 nm above a lower surface of the intermediate layer is in the first intermediate layer. A second position that is 100 nm below an upper surface of the intermediate layer is in the second intermediate layer. A value obtained by dividing a density of edge screw mixed dislocations with a Burgers vector of <11-23>/3 at the second position by a density of edge screw mixed dislocations with the Burgers vector of <11-23>/3 at the first position is at most 0.66.