A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer; a source electrode and a drain electrode; and a gate electrode that is spaced apart from the source electrode and the drain electrode, and is in contact with the second nitride semiconductor layer. The gate electrode includes: a first barrier layer that includes TaN, has a layer thickness of Z1, and forms a Schottky junction with the second nitride semiconductor layer; a second barrier layer that is disposed above and in contact with the first barrier layer, includes TiN or WN, and has a layer thickness of Z2; and a wiring layer disposed above and in contact with the second barrier layer. In the semiconductor device, 200 nm?Z1+Z2?50 nm, Z1<Z2, and 50 nm>Z1>3 nm are satisfied.

A semiconductor device is provided with: a source wiring electrically coupled to the source electrode of a transistor; a drain wiring electrically coupled to the drain electrode of the transistor; a source pad electrically coupled to the source wiring; and, a drain pad electrically coupled to the drain wiring. The source wiring includes a first source wiring section and a second source wiring section having a width greater than that of the first source wiring section. The drain wiring includes a first drain wiring section and a second drain wiring section having a width greater than that of the first drain wiring section. The source pad at least partially overlaps the second drain wiring section in plan view. The drain pad at least partially overlaps the second source wiring section in plan view.

This semiconductor device includes a substrate, a buffer layer formed on the substrate, a first semiconductor layer formed on the buffer layer, a second semiconductor layer formed on the first semiconductor layer, and a channel layer and a barrier layer formed on the second semiconductor layer. The substrate includes a nitride semiconductor doped with impurities to have semi-insulating properties or high resistance, the buffer layer includes GaN, the first semiconductor layer includes GaN doped with an acceptor, and the second semiconductor layer includes AlGaN.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Provided is a semiconductor device (1) having high heat dissipation and high operation reliability. This semiconductor device includes: a semiconductor substrate (10); a first semiconductor layer (20) that is provided on the semiconductor substrate, has a first aperture (20K), and has a first thermal conductivity; a transistor (Tr) provided on the first semiconductor layer; and a heat dissipation unit (40) that is in contact with the semiconductor substrate via the first aperture and has a second thermal conductivity higher than the first thermal conductivity.

A nitride semiconductor device includes a substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer that has a resistance higher than that of the second semiconductor layer, and a fourth semiconductor layer of the second conductivity type that are arranged sequentially from a lower side; a fifth semiconductor layer including a channel region of the first conductivity type, a portion of the fifth semiconductor layer being disposed along the inner surface of a first opening and the other portion of the fifth semiconductor layer being disposed above the fourth semiconductor layer, the first opening penetrating through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer; a sixth semiconductor layer of the second conductivity type disposed above the fifth semiconductor layer; a gate electrode; a source electrode; and a drain electrode.