A semiconductor module comprises: a first chip that includes a main transistor including an electron transit layer which serves as a main drift layer; a second chip that includes at least a part of an active clamp circuit including a clamp transistor which operates on the basis of an increase in the drain-source voltage of the main transistor; a connection member that electrically connects the main transistor and the active clamp circuit; and a sealing resin that seals the first chip, the second chip, and the connection member. The clamp transistor includes a sub-drift layer composed of a material different from that of the main drift layer.

A nitride semiconductor device includes an SiC substrate having a first principal surface and a second principal surface at an opposite side thereto, a low resistance SiC layer that is formed on the first principal surface and is lower in resistivity than the SiC substrate, a high resistance SiC layer that is formed on the low resistance SiC layer and is higher in resistivity than the low resistance SiC layer, and a nitride epitaxial layer that is disposed on the high resistance SiC layer.

A semiconductor device according to the present invention comprises: a semiconductor substrate; a GaN transistor that is formed upon the semiconductor substrate and includes a drain electrode, a source electrode, and a gate electrode; an active clamp circuit that is formed upon the semiconductor substrate, is electrically connected to the GaN transistor, and includes a clamp transistor which operates on the basis of an increase in the drain-source voltage of the GaN transistor; a drain pad that is electrically connected to the drain electrode of the GaN transistor; a main source pad that is electrically connected to the source electrode of the GaN transistor; and a gate pad that is electrically connected to the gate electrode of the GaN transistor.

A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer; a source electrode and a drain electrode; and a gate electrode that is spaced apart from the source electrode and the drain electrode, and is in contact with the second nitride semiconductor layer. The gate electrode includes: a first barrier layer that includes TaN, has a layer thickness of Z1, and forms a Schottky junction with the second nitride semiconductor layer; a second barrier layer that is disposed above and in contact with the first barrier layer, includes TiN or WN, and has a layer thickness of Z2; and a wiring layer disposed above and in contact with the second barrier layer. In the semiconductor device, 200 nmZ1+Z250 nm, Z1<Z2, and 50 nm>Z1>3 nm are satisfied.

A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

A semiconductor device according to one embodiment of the present disclosure includes a low resistance material section and a low thermal resistance material section. The low resistance material section is in contact with a barrier layer, a channel layer, and a source electrode or a drain electrode, and includes a low resistance material having a lower resistance than the channel layer. The low thermal resistance material section is in contact with the channel layer and the buffer layer, and includes a low thermal resistance material having a lower thermal resistance than the channel layer.

A semiconductor device includes a semiconductor layer having a first surface and a second surface at an opposite side thereto, a bottom gate region of a first conductivity type that is formed in the semiconductor layer, and a top gate region of the first conductivity type that is formed in a surface layer portion of the first surface of the semiconductor layer and faces the bottom gate region in a thickness direction of the semiconductor layer, the bottom gate region includes a first bottom gate region at the source region side and a second bottom gate region at the drain region side, and an interval in the thickness direction between the second bottom gate region and the top gate region is greater than an interval in the thickness direction between the first bottom gate region and the top gate region.