According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of a first band-gap material, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the first band-gap material directly adjoining the drift region and the metallization, and an anode region of a second band-gap material having a lower band-gap than the first band-gap material. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.

A protection circuit includes a first insulated gate field-effect transistor in which: a first main electrode is coupled between an external terminal and an internal circuit; a second main electrode and a gate electrode are coupled to a reference power supply; and an electric charge accumulation section configured to accumulate hot carriers is provided in a gate insulating film.

A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.

An object of the present invention is to provide high-performance highly-reliable power semiconductor device. The semiconductor device according to the present invention is provided with a semiconductor substrate of a first conductive type, a drain electrode formed on a back side of the semiconductor substrate, a drift layer of the first conductive type formed on a semiconductor substrate, a source area of the first conductive type, a current-diffused layer of the first conductive type electrically connected to the drift layer, a body layer of a second conductive type reverse to the first conductive type in contact with the source area and the current-diffused layer, a trench which pierces the source area, the body layer and the current-diffused layer, which is shallower than the body layer, and the bottom of which is in contact with the body layer, a gate insulating film formed on an inner wall of the trench, a gate electrode formed on the gate insulating film, and a gate insulating film protective layer formed between the current-diffused layer and the gate electrode.

Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

A semiconductor module comprises: a first chip that includes a main transistor including an electron transit layer which serves as a main drift layer; a second chip that includes at least a part of an active clamp circuit including a clamp transistor which operates on the basis of an increase in the drain-source voltage of the main transistor; a connection member that electrically connects the main transistor and the active clamp circuit; and a sealing resin that seals the first chip, the second chip, and the connection member. The clamp transistor includes a sub-drift layer composed of a material different from that of the main drift layer.

Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

A semiconductor device according to the present invention comprises: a semiconductor substrate; a GaN transistor that is formed upon the semiconductor substrate and includes a drain electrode, a source electrode, and a gate electrode; an active clamp circuit that is formed upon the semiconductor substrate, is electrically connected to the GaN transistor, and includes a clamp transistor which operates on the basis of an increase in the drain-source voltage of the GaN transistor; a drain pad that is electrically connected to the drain electrode of the GaN transistor; a main source pad that is electrically connected to the source electrode of the GaN transistor; and a gate pad that is electrically connected to the gate electrode of the GaN transistor.

A method of forming a semiconductor device includes forming an epitaxial layer on a substrate, forming a hard mask layer on the epitaxial layer, forming a JFET region in the epitaxial layer by using the hard mask layer and removing the hard mask layer, forming a staircase-shaped hard mask stack on the JFET region, forming a well region in the epitaxial layer by using the staircase-shaped hard mask stack, in which a bottom of the JFET region is lower than a bottom of the well region and the bottom of the well region is in contact with the JFET region and a drift region of the epitaxial layer simultaneously, forming a source region in the well region, removing the staircase-shaped hard mask stack, and forming a gate structure on the JFET region.

A method of manufacturing a semiconductor device includes forming an epitaxial layer on a substrate, forming a hard mask on the epitaxial layer, in which the hard mask includes a first portion and a second portion, with a gap therebetween, performing an oxidation process to form an oxide layer on a surface of the hard mask, forming a source region in the epitaxial layer through the gap of the hard mask, forming a well region in the epitaxial layer using the second portion of the hard mask as a mask, forming a sacrificial layer on the source region and the well region, removing the second portion of the hard mask, forming a JFET region in the epitaxial layer using the sacrificial layer as a mask, forming a dielectric layer on the JFET region, removing the sacrificial layer and forming a gate structure adjacent the dielectric layer.