A humidity detecting device includes a semiconductor substrate including at least one impurity diffusion layer, a heating unit formed by the at least one impurity diffusion layer, and a humidity detecting unit. The humidity detecting unit includes a plurality of insulating films laminated on the semiconductor substrate, a lower electrode disposed over the heating unit via a first insulating film among the insulating films, a humidity sensitive film disposed on a second insulating film among the insulating films, so as to cover the lower electrode, and an upper electrode disposed on the humidity sensitive film.

A sensor includes a semiconductor substrate, a detector disposed above the semiconductor substrate and configured to output a signal in accordance with a physical quantity, an electrostatic discharge protection circuit including a metal-oxide-semiconductor transistor, and a dummy pattern formed above the semiconductor substrate and formed of a same material as a material of a gate electrode, the gate electrode being included in the electrostatic discharge protection circuit.

The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.

A circuit includes a first bipolar junction transistor (BJT) including a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node and a second BJT including a second base, a second collector, and a second emitter, the second collector connected to the first emitter at an output node. The circuit also includes a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node. A current source device is also included that is connected in parallel with the capacitor.

A bipolar transistor having a semiconductor structure that includes a channel of semiconductor type that is the same as the collector and emitter regions. The channel is significantly shallower than the base region with which it interfaces. The semiconductor structure provides improved current gain. It also enables the device to operate, when on, selectively either with primarily unipolar conduction or with primarily bipolar conduction by control of the voltage across the emitter and collector terminals of the transistor.

Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.

A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.

A semiconductor integrated circuit for driving a control terminal of a switching device includes: a driver circuit that alternately applies a positive voltage supplied from a positive voltage source and a negative voltage supplied from a negative voltage source to the control terminal in order to switch the switching device ON and OFF; and a negative voltage clamp diode that is integrated into a semiconductor chip on which the driver circuit is formed, an anode thereof being connected to the negative voltage source and a cathode thereof being connected to the control terminal.