A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.

Semiconductor structures of Schottky devices are provided. An N-type well region and a P-type well region are formed over a P-type semiconductor substrate. A first active region is formed over the P-type well region, and includes a plurality of first fins. A second active region is formed over the N-type well region, and includes a plurality of second fins. A third active region is formed over the N-type well region, and includes a plurality of third fins. A plurality of electrodes are formed over the third active region. The electrodes, the first source/drain features and the second source/drain features are formed in the same level. An emitter region of a Schottky BJT is formed by the electrodes, a base region of the Schottky BJT is formed by the N-type well region, and a collector region of the Schottky BJT is formed by the P-type semiconductor substrate.

A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.

Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

The power semiconductor device comprises a base that includes a substrate and an epitaxial layer located above the substrate, with the base comprising a unit area and a peripheral area surrounding the unit area. A junction layer is located within the peripheral area and above the epitaxial layer. A barrier layer is located within the unit area and above the epitaxial layer. A first electrode is located on the junction layer and a second electrode is located on the barrier layer. The epitaxial layer includes a doped channel located within the peripheral area, extending between the junction layer and the base substrate. Current flows from the substrate through the doped channel and the junction layer to the first electrode.