Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a base region composed of a semiconductor on insulator material; an emitter region above the base region; and a collector region under the base region and within a cavity of a buried insulator layer.

A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

A method of fabricating a semiconductor device comprises forming, within a single process flow on a silicon on insulator (SOI) wafer, at least one of an n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET and a p channel, analog VeSFET. The method may further comprise forming, on the SOI wafer, at least one of a JFET, a BJT and a LT-MOM capacitor. The method may further comprise forming the n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET, and a p channel, analog VeSFET, according to a periodic design based on a unit circle. The method may comprise modifying a design of the semiconductor node, according to a three-dimensional architecture, to form a modified semiconductor node, and fabricating the modified semiconductor node on substrate, along with at least one other node of a different node type.

A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.

A semiconductor device includes: an active layer that is located in an SOI substrate, and in which an element included in a circuit is formed; a buried insulation layer that is located in the SOI substrate, and is in contact with the active layer; a deep trench isolation (DTI) region that is formed in the active layer to surround a whole formation region of the element in plan view, and extends from an upper surface to a lower surface of the active layer; and a first conductive film formed above the element. The DTI region has a first hole inside, and a film thickness of the first conductive film is greater than a thickness of the active layer.

A SOI lateral heterojunction Si-emitter SiGe-base bipolar transistor is provided that contains an intrinsic base region that includes a small band gap region (i.e., a silicon germanium alloy base of a first conductivity type) and a large band gap region (i.e., a silicon region of the first conductivity type) A silicon emitter of a second conductivity type that is opposite the first conductivity type is formed on the large-band gap side of the intrinsic base region and a silicon collector of the second conductivity type is formed on the small-band gap side of the intrinsic base region.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

A first of its kind polycrystalline or amorphous-based tunneling thin-film junction transistor (TJT) utilizing bipolar charge transport with a very high current density is introduced. Using the TJT architecture, this thin-film transistor (TFT) performs robustly at collector voltages at fields greater than 0.5 MV/cm with the current density output greater than 1 mA/mm without any observed electrical breakdown. Combining the principles of the tunneling emitter and the base inversion channel, the high-k dielectric/wideband gap amourphous or polycrystalline substrate/with p-type semiconductor substrate behaved most analogously to a bipolar transistor.