A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.

A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.

A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.

A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.

A semiconductor device includes an emitter, a base, and a collector. A portion of the collector is located below a trench in a substrate. A collector silicide is located on at least a portion of a bottom portion of the trench and on at least a portion of a sidewall of the trench. The collector silicide structure is electrically coupled to a collector contact structure.

An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.