An electrostatic discharge (ESD) protection device including: a substrate including: a first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region has a first conductivity type and a first doping concentration and the first and third doped regions have a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; and a doped island region disposed within the second doped region, the first and second doped terminal regions and doped island region have the second conductivity type and a third doping concentration, the third doping concentration higher than the first and second doping concentrations; and conductive terminals respectively coupled to the doped terminal regions; and an insulation layer arranged on the substrate between the conductive terminals and covering at least the second doped region.

An electrostatic discharge (ESD) protection device including: a substrate including: a first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region has a first conductivity type and a first doping concentration and the first and third doped regions have a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; and a doped island region disposed within the second doped region, the first and second doped terminal regions and doped island region have the second conductivity type and a third doping concentration, the third doping concentration higher than the first and second doping concentrations; and conductive terminals respectively coupled to the doped terminal regions; and an insulation layer arranged on the substrate between the conductive terminals and covering at least the second doped region.

Embodiments of the disclosure provide a lateral bipolar transistor structure with an emitter/collector (E/C) contact to a doped semiconductor well and related methods. A bipolar transistor structure according to the disclosure may include a doped semiconductor well over a semiconductor substrate. An insulative region is on the doped semiconductor well. A base layer is on the insulative region, and an emitter/collector (E/C) layer on the insulative region and adjacent a first sidewall of the base layer. An E/C contact to the doped semiconductor well includes a lower portion adjacent the insulative region and an upper portion adjacent and electrically coupled to the E/C layer.

Embodiments of the disclosure provide a lateral bipolar transistor structure with an emitter/collector (E/C) contact to a doped semiconductor well and related methods. A bipolar transistor structure according to the disclosure may include a doped semiconductor well over a semiconductor substrate. An insulative region is on the doped semiconductor well. A base layer is on the insulative region, and an emitter/collector (E/C) layer on the insulative region and adjacent a first sidewall of the base layer. An E/C contact to the doped semiconductor well includes a lower portion adjacent the insulative region and an upper portion adjacent and electrically coupled to the E/C layer.

For example, a semiconductor device includes one or more first subcontacts electrically conducted to a substrate. At least one of the one or more first subcontacts is formed in an element arrangement region, and has a lower impedance than the substrate. Preferably, at least one of the one or more first subcontacts is adjacent to a circuit element formed in the element arrangement region. Preferably, on the substrate, which is of a first conductivity type, an epilayer of a second conductivity type is formed, and the one or more first subcontacts include a first line having a lower impedance than the substrate, and a semiconductor region of the first conductivity type penetrating through the epilayer to electrically conduct the first line and the substrate to each other.

Embodiments of the disclosure provide a bipolar transistor structure including a semiconductor fin on a substrate. The semiconductor fin has a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. A first emitter/collector (E/C) material is adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin. The first E/C material has a second doping type opposite the first doping type. A second E/C material is adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin. The second E/C material has the second doping type. A width of the first E/C material is different from a width of the second E/C material.

In order to reduce costs as well as to effectively dissipate heat in certain RF circuits, a semiconductor device of the circuit can include one or more active devices such as transistors, diodes, and/or varactors formed of a first semiconductor material system integrated onto (e.g., bonded to) a base substrate formed of a second semiconductor material system that includes other circuit components. The first semiconductor material system can, for example, be the III-V or III-N semiconductor system, and the second semiconductor material system can, for example be silicon.

A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

A semiconductor device includes an emitter, a base, and a collector. A portion of the collector is located below a trench in a substrate. A collector silicide is located on at least a portion of a bottom portion of the trench and on at least a portion of a sidewall of the trench. The collector silicide structure is electrically coupled to a collector contact structure.