Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.

The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.

A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

A III-V semiconductor die for die crack detection is provided. The III-V semiconductor die includes a device area. The III-V semiconductor die further includes a doped semiconductor ring region. The doped semiconductor ring region surrounds the device area. At least one active device or at least one passive device is formed in the device area of the III-V semiconductor die.

A III-V semiconductor die for die crack detection is provided. The III-V semiconductor die includes a device area. The III-V semiconductor die further includes a doped semiconductor ring region. The doped semiconductor ring region surrounds the device area. At least one active device or at least one passive device is formed in the device area of the III-V semiconductor die.

Heterostructures include a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions.

A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.

A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.