The present disclosure generally relates to dopant profile control in a heterojunction bipolar transistor (HBT). In an example, a semiconductor device structure includes a semiconductor substrate and an HBT. The HBT includes a collector region, a base region, and an emitter region. The base region is disposed on or over the collector region. The emitter region is disposed on or over the base region. The base region is disposed on or over the semiconductor substrate and includes a heteroepitaxial sub-layer. The heteroepitaxial sub-layer is doped with a dopant. A concentration gradient of the dopant increases from a region in a layer adjoining and overlying the heteroepitaxial sub-layer to a peak concentration in the heteroepitaxial sub-layer without decreasing between the region and the peak concentration.

The present disclosure generally relates to dopant profile control in a heterojunction bipolar transistor (HBT). In an example, a semiconductor device structure includes a semiconductor substrate and an HBT. The HBT includes a collector region, a base region, and an emitter region. The base region is disposed on or over the collector region. The emitter region is disposed on or over the base region. The base region is disposed on or over the semiconductor substrate and includes a heteroepitaxial sub-layer. The heteroepitaxial sub-layer is doped with a dopant. A concentration gradient of the dopant increases from a region in a layer adjoining and overlying the heteroepitaxial sub-layer to a peak concentration in the heteroepitaxial sub-layer without decreasing between the region and the peak concentration.

A semiconductor device includes a semiconductor substrate, a first semiconductor region of a first semiconductor type, formed within the semiconductor substrate, wherein the first semiconductor region includes a first doped region formed in a lower portion of the first semiconductor region and a second doped region formed over the first doped region in an upper portion of the first semiconductor region. A defect layer having an upper surface formed in an upper portion of the first doped region. A second semiconductor region of a second semiconductor type is formed over the first semiconductor region.

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.

A semiconductor device and a method of making a semiconductor device are described. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer having a top surface and a side surface, a second terminal having a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further includes a contact positioned to overlap with the top surface and the side surface of the first raised semiconductor layer.

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer having a top surface and a side surface, a second terminal having a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further includes a contact positioned to overlap with the top surface and the side surface of the first raised semiconductor layer.

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.