H01L29/737

NON-SELF-ALIGNED LATERAL BIPOLAR JUNCTION TRANSISTORS

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

Semiconductor device

A semiconductor device includes a collector layer, a base layer, and an emitter layer that are disposed above a substrate. An emitter mesa layer is disposed on a partial region of the emitter layer. In a plan view, the base electrode is disposed in or on a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In the plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located in an end portion of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.

Semiconductor device

A semiconductor device includes a collector layer, a base layer, and an emitter layer that are disposed above a substrate. An emitter mesa layer is disposed on a partial region of the emitter layer. In a plan view, the base electrode is disposed in or on a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In the plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located in an end portion of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.

BIPOLAR JUNCTION TRANSISTORS INCLUDING A STRESS LINER
20230063900 · 2023-03-02 ·

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.

BIPOLAR JUNCTION TRANSISTORS INCLUDING A STRESS LINER
20230063900 · 2023-03-02 ·

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.

LATERAL BIPOLAR TRANSISTOR STRUCTURE WITH BASE OVER SEMICONDUCTOR BUFFER AND RELATED METHOD
20230061482 · 2023-03-02 ·

The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

LATERAL BIPOLAR TRANSISTOR STRUCTURE WITH BASE OVER SEMICONDUCTOR BUFFER AND RELATED METHOD
20230061482 · 2023-03-02 ·

The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

FIN-BASED LATERAL BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE AND METHOD

A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

Heterojunction Bipolar Transistor and Method of Manufacturing the Same
20230163193 · 2023-05-25 ·

A heterojunction bipolar transistor includes a first emitter electrode, a second emitter electrode, and a third emitter electrode that are formed on an emitter cap layer. The first emitter electrode has an area greater than or equal to an area of the emitter cap layer in a plan view, and is made of a tungsten alloy. The second emitter electrode is formed on the first emitter electrode, is made of a metal that contains W and is different from a metal of the first emitter electrode, and has an area greater than an area of the first emitter electrode in a plan view.

Heterojunction Bipolar Transistor and Method of Manufacturing the Same
20230163193 · 2023-05-25 ·

A heterojunction bipolar transistor includes a first emitter electrode, a second emitter electrode, and a third emitter electrode that are formed on an emitter cap layer. The first emitter electrode has an area greater than or equal to an area of the emitter cap layer in a plan view, and is made of a tungsten alloy. The second emitter electrode is formed on the first emitter electrode, is made of a metal that contains W and is different from a metal of the first emitter electrode, and has an area greater than an area of the first emitter electrode in a plan view.