A novel and useful modified semiconductor fabrication technique for realizing reliable semiconductor quantum structures. Quantum structures require a minimization of the parasitic capacitance of the control gate and the quantum well. The modified semiconductor process eliminates the fabrication of the metal, contact, and optionally the raised diffusion layers from the quantum wells, thereby resulting in much lower well and gate capacitances and therefore larger Coulomb blockade voltages. This allows easier implementation of the electronic control circuits in that they can have larger intrinsic noise and relaxed analog resolution. Several processes are disclosed including implementations of semiconductor quantum structures with tunneling through an oxide layer as well as tunneling through a local well depleted region. These techniques can be used in both planar semiconductor processes and 3D, e.g., FinFET, semiconductor processes. A dedicated process masking step is used for realizing the raised diffusions. In addition, the edge of the raised diffusion layer may be placed either in the gate region or the active layer region.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

Embodiments relate to a Gaussian synapse device configured so that its transfer characteristics resemble a Gaussian distribution. Embodiments of the Gaussian synapse device include an n-type field-effect transistor (FET) and p-type FET with a common contact so that the two FETs are connected in series. Some embodiments include a global back-gate contact and separate top-gate contact to obtain dual-gated FETs. Some embodiments include two different 2D materials used in the channel to generate the two FETs, while some embodiments use a single ambipolar transport material. In some embodiments, the dual-gated structure is used to dynamically control the amplitude, mean and standard deviation of the Gaussian synapse. In some embodiments, the Gaussian synapse device can be used as a probabilistic computational device (e.g., used to form a probabilistic neural network).

A semiconductor device includes a semiconductor part, first and second electrodes, and a control electrode. The semiconductor part is provided between the first and second electrodes. The control electrode is provided in a trench of the semiconductor part between the semiconductor part and the second electrode. The semiconductor part includes first to third layers. The first layer of a first conductivity type extends between the first and second electrodes. The second layer of a second conductivity type is provided between the first layer and the second electrode. The second layer is connected to the second electrode. The third layer of the second conductivity type is provided between the second layer and the control electrode. The third layer includes a second-conductivity-type impurity with a higher concentration than a second-conductivity-type impurity of the second layer. The third layer contacts the second electrode, and is electrically connected to the second electrode.

A parallel structure comprising source/drain and channel layers alternately stacked on a substrate, and gate stacks formed around peripheries of the channel layers. Each of the channel layers, the source/drain layers on upper and lower sides of the channel layer, and the gate stack formed around the channel layer, form a semiconductor device. In each semiconductor device, one of the source/drain layers is in contact with a first electrically-conductive channel disposed on an outer periphery of the active region, the other is in contact with a second electrically-conductive channel on the outer periphery of the active region, and the gate stack is in contact with a third electrically-conductive channel disposed on the outer periphery of the active region. The first electrically-conductive channel is common to the semiconductor devices, the second electrically-conductive channel is common to the semiconductor devices, and the third electronically-conductive channel is common to the semiconductor devices.

Structures for a diode and methods of fabricating a structure for a diode. The structure includes a layer comprised of a semiconductor material. The layer includes a first section, a second section, and a third section laterally positioned between the first section and the second section. The structure includes a first terminal having a raised semiconductor layer on the first section of the layer, a second terminal including a portion on the second section of the layer, and a gate on the third section of the layer.

A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.

In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

An apparatus includes a biosensor integrated circuit (IC) chip with sensing zones and/or well structures configured to receive a liquid with biological analytes. The chip includes passivation and etch stop layers with an opening over a channel layer and an array of liquid gated field effect transistors with a 2D channel disposed on a dielectric oxide layer. A conductive drain and a conductive source form edge and/or top side contacts with opposite ends of the 2D channel. The chip further includes reference electrodes formed in a metal layer, configured to contact the liquid, and disposed at a horizontal distance apart from the graphene channels. The transistors are operable to enable a set of measurements to sense parameters of the biological analytes based on changes in a shape of Id-Vgs transconductance curves. A system and a method have similar structures and perform the functions of the apparatus.

A semiconductor memory device that may include a substrate, an array of memory cells arranged in rows and columns, bit lines and word lines. The memory cells each may include a pillar-shaped active region extending vertically, which includes source/drain regions at upper and lower ends respectively and a channel region between the source/drain regions. The channel region may include a single-crystalline semiconductor material. The memory cells each may further include a gate stack formed around a periphery of the channel region. Each of the bit lines is located below a corresponding column, and electrically connected to the lower source/drain regions of the respective memory cells in the corresponding column. Each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding row.