A semiconductor device includes a silicon substrate, a first layer, a second layer, a barrier metal, and a gate pad. The first layer is formed of an oxide film provided on an upper surface of the silicon substrate. The second layer is a layer at least selectively having a projecting and recessed part on an upper surface of the first layer, the projecting and recessed part having a projection and recess deeper than a projection and recess occurring when the layer is formed in a planar shape. The barrier metal is formed on an upper surface of the second layer according to a shape of the projecting and recessed part. The gate pad is in close contact with the silicon substrate via the barrier metal.

Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.

A bus assembly includes a planar first bus, a second bus including a first planar bus section on the first bus and a second planar bus section connected to the first planar bus section and offset from the first planar bus section, and a third bus comprising a third planar bus section disposed between the first bus and the second planar bus section, and a fourth planar bus section connected to the third planar bus section, offset from third planar bus section, and disposed on the first planar bus section.

Systems and methods for building passive and active electronics with diamond-like carbon (DLC) coatings are provided herein. DLC may be layered upon substrates to form various components of electronic devices. Passive components such as resistors, capacitors, and inductors may be built using DLC as a dielectric or as an insulating layer. Active components such as diodes and transistors may be built with the DLC acting substantially like a semiconductor. The amount of sp.sup.2 and sp.sup.3 bonded carbon atoms may be varied to modify the properties of the DLC for various electronic components.

An insulated gate bipolar transistor and a fabrication method therefor, wherein the fabrication method for the insulated gate bipolar transistor comprises the following steps: implanting hydrogen ions, arsenic ions, or nitrogen ions into a substrate from a back surface of the insulated gate bipolar transistor so as to form an n-type heavily doped layer (202) of a reverse conduction diode, the reverse conduction diode being a reverse conduction diode built into the insulated gate bipolar transistor. The described fabrication method and the obtained insulated gate bipolar transistor from a recombination center in an n+ junction of the reverse conduction diode, thereby accelerating the reverse recovery speed of the built-in reverse conduction diode, shortening the reverse recovery time thereof, and improving the performance of the insulated gate bipolar transistor.

According to the disclosure, a semiconductor device includes a semiconductor substrate including an IGBT region and a diode region, a first electrode provided on an upper surface of the semiconductor substrate and a second electrode provided on a back surface of the semiconductor substrate, wherein the diode region includes an n-type drift layer, a p-type anode layer provided on an upper surface side of the drift layer, and an n-type cathode layer provided on a back surface side of the drift layer, a lifetime control region having crystal defect density higher than crystal defect density of other portions of the drift layer and including protons is provided on a back surface side relative to a center in a thickness direction of the semiconductor substrate among the drift layer, and a maximum value of donor concentration of the lifetime control region is equal to or less than 1.0×10.sup.15/cm.sup.3.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer; depositing a second epitaxial layer on the first epitaxial layer; forming a single termination trench in the second epitaxial layer; and filling the termination trench with a dielectric. A depth of the termination trench is greater than 10 microns. In another aspect, a transistor includes a first epitaxial layer; a second epitaxial layer on the first epitaxial layer; and a single termination trench in the second epitaxial layer. The termination trench is greater than 10 microns and is filled with a dielectric.

Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n.sup.+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.

The semiconductor device according to the present disclosure has features (1) to (3) below. The feature (1) is that “a lower surface of an on-chip bonding material has a shape matching a surface shape of a main current wiring connection region in plan view”. The feature (2) is that “an emitter sense wiring is directly connected to a side surface of the main current wiring connection region”. The feature (3) is that “an IGBT chip has an ineffective region in which the IGBT does not function in a region below an emitter sense pad and the emitter sense wiring”.