A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.

An ESD Protection Device includes a semiconductor body including a substrate, conductivity regions, and emitter and collector portions. Laterally adjacent first and second conductivity regions are arranged at least partially within the semiconductor body. The emitter and collector portions are disposed in contact with and arranged over the first and second conductivity regions respectively. The third conductivity region is disposed between the second conductivity region and the collector portion. The first and third conductivity regions have a first conductivity type. The second conductivity region, and the emitter and collector portions have a second conductivity type different from the first conductivity type. When an electrostatic discharge level exceeds a predetermined level, a first discharge current passes between the emitter portion and the collector portion through the first and second conductivity regions. A second discharge current subsequently occurs and passes between the first and third conductivity regions through the second conductivity region.

An electrical configuration contains at least one submodule which has a first and a second outer electrical terminal. The configuration further has a bypass switching device, which is electrically connected between the first and second terminals and in the on-state causes an electrical short-circuit in at least one current flow direction between the two outer terminals. The bypass switching device has a thyristor with an anode terminal, a cathode terminal and a trigger terminal and is connected by its anode terminal to one of the two outer terminals and by its cathode terminal to the other of the two outer terminals. A triggering device is connected to the trigger terminal of the thyristor for triggering the thyristor, and a switch is provided which in the on-state connects the anode terminal of the thyristor to the trigger terminal of the thyristor.

The present invention relates to an electrical circuit arrangement with an active discharge circuit including at least one electrical switching element, by means of which the circuit arrangement can be discharged in controlled manner. The circuit arrangement includes a RC snubber element with capacitor and resistor for damping voltage or current peaks in the circuit arrangement, wherein the electrical switching element is integrated in the RC snubber element and connected in parallel to the capacitor of the RC snubber. This enables the discharge circuit to be designed in a manner that is economical in terms of space and cost. The discharge circuit uses the heat sink for the RC snubber element and therefore does not need any additional heat dissipation systems.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.

A silicon-controlled rectifier includes a semiconductor body including a first main surface, an active device region, a first, a second, a third and a fourth surface contact area at the first main surface and arranged directly one after another along a first lateral direction, wherein the semiconductor body is electrically contacted at each of the first to fourth surface contact areas, and a first, a second, a third and a fourth SCR region, wherein the first and third SCR regions are of a first conductivity type and directly adjoin the first and third surface contact areas, respectively, and wherein the second and fourth SCR regions are of a second conductivity type and directly adjoin the second and fourth surface contact areas, respectively, wherein the first SCR region is electrically connected to the fourth SCR region, and the second SCR region is electrically connected to the third SCR region.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor additionally comprises first and second crystalline conductive or semiconductive oxide electrodes on opposing sides of the polar layer, wherein the polar layer has a lattice constant that is matched within about 20% of a lattice constant of one or both of the first and second crystalline conductive or semiconductive oxide electrodes. The first crystalline conductive or semiconductive oxide electrode serves as a template for growing the polar layer thereon, such that at least a portion of the polar layer is pseudomorphically formed on the first crystalline conductive or semiconductive oxide electrode.

An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.