Provided are an ESD protection diode and an electronic device including the same. An ESD protection diode and an electronic device including the same according to an embodiment of the inventive concept include first to fifth wells. The first well is connected to a first voltage terminal. The second well is connected to a second voltage terminal. The third well is connected to the input/output terminal. The fourth well is disposed between the first well and the third well, and the fifth well is disposed between the second well and the third well. The first to third wells are N-type wells, and the fourth and fifth wells are P-type wells. The first well includes a first N+ diffusion region and the second well includes a second N+ diffusion region. The fourth well includes a first P+ diffusion region and the fifth well includes a second P+ diffusion region. According to an embodiment of the inventive concept, an internal circuit is protected fro an ESD pulse applied to a plurality of terminals and holding voltage is increased.

According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.

A light-emitting component includes a substrate, a light-emitting element, a thyristor, and a light-transmission reduction layer. The light-emitting element is disposed on the substrate. The thyristor causes the light-emitting element to emit light or causes an amount of light emitted by the light-emitting element to increase, upon entering an on-state. The light-transmission reduction layer is disposed between the light-emitting element and the thyristor such that the light-emitting element and the thyristor are stacked, and suppresses light emitted by the thyristor from passing therethrough.

An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.

A power semiconductor device (1) comprises a gate-commutated thyristor cell (20) including a cathode electrode (2), a cathode region (9) of a first conductivity type, a base layer (8) of a second conductivity type, a drift layer (7) of the first conductivity type, an anode layer (5) of the second conductivity type, an anode electrode (3) and a gate electrode (4). The base layer (8) comprises a cathode base region (81) located between the cathode region (9) and the drift layer (7) and having a first depth (D1), a gate base region (82) located between the gate electrode (4) and the drift layer (7) and having a second depth (D2), and an intermediate base region (83) located between the cathode base region (81) and the gate base region (82) and having two different values of a third depth (D3) being between the first depth (D1) and the second depth (D2).

A transient-voltage-suppression (TVS) diode device and a method of fabricating the same are disclosed. The TVS diode device includes a substrate. A second conductivity type first epitaxial layer is disposed over the substrate. A second conductivity type second epitaxial layer is disposed between the second conductivity type first epitaxial layer and the substrate. A plurality of trench isolation features divides the substrate into a first active region including a second conductivity type doped well region disposed in the second conductivity type first epitaxial layer. A first conductivity type doped well region and a first conductivity type buried layer are disposed in the second conductivity type second epitaxial layer. The second conductivity type doped well region and the first conductivity type buried layer collectively form a Zener diode.

A layered structure includes a thyristor and a light-emitting element. The thyristor at least includes four layers. The four layers are an anode layer, a first gate layer, a second gate layer, and a cathode layer arranged in this order. The light-emitting element is disposed such that the light-emitting element and the thyristor are connected in series. The thyristor includes a semiconductor layer having a bandgap energy smaller than bandgap energies of the four layers.

A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.

An ESD protection circuit and integrated circuit for a broadband circuit are disclosed. The ESD protection circuit includes a silicon-controlled rectifier, an inductor and a trigger unit. The silicon-controlled rectifier is formed by four semiconductor materials and includes a first end, a second end and a third end. The first end is coupled with a first P-type semiconductor material and a signal input end. The second end is coupled with a second N-type semiconductor material. The third end is coupled with a second P-type semiconductor material. One end of the inductor is coupled with the signal input end and the first end, and the other end thereof is coupled with a signal output end and a high-frequency circuit. One end of the trigger unit is coupled with the signal output end and the high-frequency circuit, and the other end thereof is coupled with the third end.

Provided is a device including a first clamp circuit electrically connected between a first node and a second node, and a second clamp circuit electrically connected between the second node and a third node, wherein the first clamp circuit includes a first silicon controlled rectifier (SCR) including a first region of a first conductivity type electrically connected to the first node, a second region of a second conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type electrically connected to the second node, and a first gate electrode disposed over a channel region including a junction of the second region and the third region between the first region and the fourth region.