A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.

A transient voltage suppressor (TVS) circuit includes a first finger and a second finger of semiconductor regions arranged laterally along a first direction on a major surface of a semiconductor layer, the first finger and second finger extending in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The semiconductor regions in a first portion of the first and second fingers form a silicon controlled rectifier and the semiconductor regions in a second portion of the first and second fingers form a P-N junction diode.

It is aimed to realize both of reserving a channel formation region and suppressing a latch-up. A semiconductor device is provided, including: a semiconductor substrate; a plurality of trench portions provided at a front surface side of the semiconductor substrate, each of which has a portion extending in an extending direction; and a first conductivity-type emitter region and a second conductivity-type contact region provided between adjacent two trench portions and exposed on a front surface of the semiconductor substrate alternately in the extending direction, wherein on the front surface of the semiconductor substrate, a length of the emitter region at a central position between the two trench portions is shorter than a length of the emitter region at portions contacting the trench portions, and on the front surface of the semiconductor substrate, at least a part of a boundary of the emitter region has a curved shape.

A light-emitting component includes a light-emitting element, a thyristor, and a light-absorbing layer. The thyristor includes a semiconductor layer having a bandgap energy smaller than or equal to a bandgap energy equivalent to a wavelength of light emitted by the light-emitting element. The thyristor causes the light-emitting element to emit light or causes an amount of light emitted by the light-emitting element to increase, upon entering an on-state. The light-absorbing layer is disposed between the light-emitting element and the thyristor such that the light-emitting element and the thyristor are stacked. The light-absorbing layer absorbs the light emitted by the light-emitting element.

A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.

An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

An integrated circuit includes at least one input-output pad and a terminal intended to be connected to a source of a reference potential and further including a protection structure including a thyristor forward-connected between the pad and the terminal. The thyristor includes a first resistor between its cathode gate and the terminal. At least one Zener diode is disposed between the thyristor and the pad. The anode of the Zener diode is connected to the cathode gate of the thyristor and the cathode of the Zener diode is connected to the pad via at least one second resistor. The junction of the Zener diode is different from the junctions of the PNPN structure of the thyristor.

A transient voltage suppressor (TVS) circuit includes a P-N junction diode and a silicon controlled rectifier (SCR) formed integrated in a lateral device structure of a semiconductor layer. The lateral device structure includes multiple fingers of semiconductor regions arranged laterally along a first direction on a major surface of the semiconductor layer, defining current conducting regions between the fingers. The current paths for the SCR and the P-N junction diode are formed in each current conducting region but the current path for the SCR is predominantly separated from the current path for the P-N junction diode in each current conducting region in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The TVS device of the present invention realizes low capacitance at the protected node. The TVS device is suitable for protecting data pins of an integrated circuit, especially when the data pins are used in high speed applications.

A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.

A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.