A power electronic arrangement includes a semiconductor switch structure configured to assume a forward conducting state. A steady-state current carrying capability of the semiconductor switch structure in the forward conducting state is characterized by a nominal current. The semiconductor switch structure is configured to conduct, in the forward conducting state, at least a part of a forward current in a forward current mode of the power electronic arrangement. A diode structure electrically connected in antiparallel to the semiconductor switch structure is configured to conduct at least a part of a reverse current in a reverse mode of the power electronic arrangement. A thyristor structure electrically connected in antiparallel to the semiconductor switch structure has a forward breakover voltage than a diode on-state voltage of the diode structure at a critical diode current value, the critical diode current value amounting to at most five times the nominal current.

Device structures including a silicon-controlled rectifier and methods of forming a device structure including a silicon-controlled rectifier. The device structure comprises a first well and a second well in a semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite from the first conductivity type. The second well adjoins the first well along an interface. A third doped region includes a first portion in the first well and a second portion in the second well, and a gate structure that overlaps with a portion of the second well.

A transient voltage suppressor (TVS) circuit includes a first finger and a second finger of semiconductor regions arranged laterally along a first direction on a major surface of a semiconductor layer, the first finger and second finger extending in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The semiconductor regions in a first portion of the first and second fingers form a silicon controlled rectifier and the semiconductor regions in a second portion of the first and second fingers form a P-N junction diode.

The present application discloses a low voltage triggering silicon controlled rectifier which includes: an N well and a P well forming a PN junction, a first P+ region formed in the N well and connected to an anode, and a first N+ region formed in the P well and connected to a cathode. A second P+ region is formed in the N well at the PN junction and diffuses into the P well. A second N+ region is formed in the P well at the PN junction and diffuses into the N well. A first gate structure connected to the anode is formed at the surface of the N well between the first and second P+ regions; and a second gate structure connected to the cathode is formed at the surface of the P well between the first and second N+ regions.

A method for depositing a metal chalcogenide on a substrate by cyclical deposition is disclosed. The method may include, contacting the substrate with at least one metal containing vapor phase reactant and contacting the substrate with at least one chalcogen containing vapor phase reactant. Semiconductor device structures including a metal chalcogenide deposited by the methods of the disclosure are also provided.

Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate.

An electronic device can include a bidirectional HEMT. In an aspect, the electronic device can include a pair of switch gate and blocking gate electrodes, wherein the switch gate electrodes are not electrically connected to the blocking gate electrodes, and the first blocking, first switch, second blocking, and second switch gate electrodes are on the same die. In another aspect, the electronic device can include shielding structures having different numbers of laterally extending portions. In a further aspect, the electronic device can include a gate electrode and a shielding structure, wherein a portion of the shielding structure defines an opening overlying the gate electrode.

A method for depositing a metal chalcogenide on a substrate by cyclical deposition is disclosed. The method may include, contacting the substrate with at least one metal containing vapor phase reactant and contacting the substrate with at least one chalcogen containing vapor phase reactant. Semiconductor device structures including a metal chalcogenide deposited by the methods of the disclosure are also provided.

Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.

A transient voltage suppressor (TVS) circuit includes a first finger and a second finger of semiconductor regions arranged laterally along a first direction on a major surface of a semiconductor layer, the first finger and second finger extending in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The semiconductor regions in a first portion of the first and second fingers form a silicon controlled rectifier and the semiconductor regions in a second portion of the first and second fingers form a P-N junction diode.