Disclosed are film packages and methods of fabricating package modules. The film package includes a film substrate that includes a chip region and a peripheral region facing each other in a first direction, a plurality of output pads that are arranged in the first direction on the chip region and on the peripheral region, and a semiconductor chip on the chip region and electrically connected to the output pads. The output pads on the chip region are arranged at regular first intervals along the first direction. The output pads include a plurality of first output pads that are arranged at a first pitch along the first direction on the chip region and a plurality of second output pads on the peripheral region. The second output pads are arranged at a second pitch greater than the first pitch of the first output pads.

A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.

A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.

A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.

The present invention relates to novel inventive compound device structures, enabling charged-based logic gates. In particular, a switched p-channel and/or n-channel current field effect transistor, a solid state device based on a complimentary pair of a switched p-channel and n-channel current field effect transistors, and/or a solid state device based on a complimentary pair of a p-channel and n-channel current field effect transistors are used for constructing such logic gates. The switched current field effect transistor comprising a source and a drain, wherein the source and drain defines a channel, a diffusion that divides the channel into a source channel segment between the source and the diffusion and a drain channel segment between the drain and the diffusion, a source channel gate that is coupled to the source channel, and a drain channel gate that coupled to the drain channel. These novel device structures provide various improvements over the conventional devices.

The present invention relates to novel inventive compound device structures, enabling charged-based logic gates. In particular, a switched p-channel and/or n-channel current field effect transistor, a solid state device based on a complimentary pair of a switched p-channel and n-channel current field effect transistors, and/or a solid state device based on a complimentary pair of a p-channel and n-channel current field effect transistors are used for constructing such logic gates. The switched current field effect transistor comprising a source and a drain, wherein the source and drain defines a channel, a diffusion that divides the channel into a source channel segment between the source and the diffusion and a drain channel segment between the drain and the diffusion, a source channel gate that is coupled to the source channel, and a drain channel gate that coupled to the drain channel. These novel device structures provide various improvements over the conventional devices.

A semiconductor device includes a substrate, an inter-layer dielectric layer, a contact plug, and a contact hole liner. The substrate has a source/drain region. The inter-layer dielectric layer is over the substrate and has a contact hole therein. The contact plug is electrically connected to the source/drain region through the contact hole of the inter-layer dielectric layer. The contact hole liner extends between the contact plug and a sidewall of a first portion of the contact hole. The contact hole liner terminates prior to reaching a second portion of the contact hole. The first portion is between the second portion and the source/drain region.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

A charge sensing device for sensing charge variations in a charge storage area includes: a TFET having at least one sense gate; and a capacitive coupling for coupling the charge storage area with the sense gate.