A charge sensing device for sensing charge variations in a charge storage area includes: a TFET having at least one sense gate; and a capacitive coupling for coupling the charge storage area with the sense gate.

A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.

The present disclosure relates to a CMOS image sensor having a pixel device on a deep trench isolation (DTI) structure, and an associated method of formation. In some embodiments, a deep trench isolation (DTI) structure is disposed at a peripheral of a pixel region, extending from a back-side of the substrate to a position within the substrate. A pixel device is disposed at the front-side of the substrate directly overlying the DTI structure. The pixel device comprises a pair of source/drain (S/D) regions disposed within the substrate and reaching on a top surface of the DTI structure. By forming the disclosed pixel device directly overlying the DTI structure to form a SOI device structure, short channel effect is reduced because of the room for pixel device and also because the insulation layer underneath the pixel device. Thus higher device performance can be realized.

A method for forming a backside illuminated image sensor with a three-dimensional transistor structure is provided, where forming a gate of the three-dimensional transistor structure includes: forming a source follower transistor and/or a reset transistor with a three-dimensional transistor structure, wherein the source follower transistor and/or the reset transistor correspond to a protruding structure; and forming an insulating sidewall around the protruding structure, forming a groove between the insulating sidewall and a channel region of a transistor corresponding to the protruding structure, and forming a gate of the transistor in the groove, wherein the gate of the transistor is isolated by the insulating sidewall.

A photosensitive detection module is provided, comprising a photosensitive circuit, wherein the photosensitive circuit comprises a first resistive element, a second resistive element, a third resistive element, a fourth resistive element to form a resistor bridge, a first input terminal connected to a node between the first resistive element and the third resistive element, a second input terminal connected to a node between the second resistive element and the fourth resistive element, a first output terminal connected to a node between the first resistive element and the second resistive element, and a second output terminal connected to a node between the third resistive element and the fourth resistive element. All four resistive elements have an identical initial resistance value. The first resistive element and the fourth resistive element are photosensitive resistive elements.

A photosensitive detection module is provided, comprising a photosensitive circuit, wherein the photosensitive circuit comprises a first resistive element, a second resistive element, a third resistive element, a fourth resistive element to form a resistor bridge, a first input terminal connected to a node between the first resistive element and the third resistive element, a second input terminal connected to a node between the second resistive element and the fourth resistive element, a first output terminal connected to a node between the first resistive element and the second resistive element, and a second output terminal connected to a node between the third resistive element and the fourth resistive element. All four resistive elements have an identical initial resistance value. The first resistive element and the fourth resistive element are photosensitive resistive elements.

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

The present invention relates to a charge sensing device for sensing charge variations in a charge storage area including: a TFET having at least one sense gate; a capacitive coupling for coupling the charge storage area with the sense gate.

The present invention relates to a charge sensing device for sensing charge variations in a charge storage area including: a TFET having at least one sense gate; a capacitive coupling for coupling the charge storage area with the sense gate.