H01L29/768

Semiconductor device, memory circuit, method of manufacturing semiconductor device
10269867 · 2019-04-23 · ·

A semiconductor device of the technology includes a first diffusion section (22), a second diffusion section (21), a channel section (23), a gate section (24), and a stress application section (31, 32, or 33). In a semiconductor layer (10) having a groove (10A), the first diffusion section (22) is formed at or in the vicinity of a bottom of the groove (10A), the second diffusion section (21) is formed at an upper end of the groove (10A), and the channel section (23) is formed between the first diffusion section (22) and the second diffusion section (21). The gate section (24) is buried in the groove (10A) at a position opposing the channel section (23). The stress application section (31, 32, or 33) applies one of compressive stress and tensile stress to the channel section (23) in a normal direction to the semiconductor layer (10).

Semiconductor device, memory circuit, method of manufacturing semiconductor device
10269867 · 2019-04-23 · ·

A semiconductor device of the technology includes a first diffusion section (22), a second diffusion section (21), a channel section (23), a gate section (24), and a stress application section (31, 32, or 33). In a semiconductor layer (10) having a groove (10A), the first diffusion section (22) is formed at or in the vicinity of a bottom of the groove (10A), the second diffusion section (21) is formed at an upper end of the groove (10A), and the channel section (23) is formed between the first diffusion section (22) and the second diffusion section (21). The gate section (24) is buried in the groove (10A) at a position opposing the channel section (23). The stress application section (31, 32, or 33) applies one of compressive stress and tensile stress to the channel section (23) in a normal direction to the semiconductor layer (10).

Solid-state image pickup device
10249659 · 2019-04-02 · ·

A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

Tunnel field effect transistor having anisotropic effective mass channel

A tunnel field effect transistor (TFET) includes a substrate, heavily doped source and drain regions disposed at opposite ends of a channel region forming a PiN or NiP structure, the channel region including a first substantially parallelogram portion having a first length defined along a longitudinal axis extending from the source region to the drain region and a second substantially parallelogram portion having a second length defined along the longitudinal axis larger than the first length, the TFET device having an effective channel length that is an average of the first and second lengths. The channel region includes a channel material with a first effective mass along a longitudinal axis extending from the source region to the drain region and a second effective mass along a lateral axis perpendicular to the longitudinal axis, the first effective mass being greater than the second effective mass.

Methods of manufacturing semiconductor devices including gate pattern, multi-channel active pattern and diffusion layer

A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Organic thin film transistor, method of manufacturing organic thin film transistor, organic thin film transistor material, organic thin film transistor composition, organic semiconductor film, and compound

An object of the present invention is to provide an organic thin film transistor that has an organic semiconductor film manufactured by using a compound having excellent solubility to an organic solvent and that has excellent carrier mobility, a novel compound, an organic thin film transistor material, an organic semiconductor film, an organic thin film transistor composition, and a method of manufacturing an organic thin film transistor using this. The organic thin film transistor according to the present invention has an organic semiconductor film containing a compound represented by Formula (1). ##STR00001##

Organic thin film transistor, method of manufacturing organic thin film transistor, organic thin film transistor material, organic thin film transistor composition, organic semiconductor film, and compound

An object of the present invention is to provide an organic thin film transistor that has an organic semiconductor film manufactured by using a compound having excellent solubility to an organic solvent and that has excellent carrier mobility, a novel compound, an organic thin film transistor material, an organic semiconductor film, an organic thin film transistor composition, and a method of manufacturing an organic thin film transistor using this. The organic thin film transistor according to the present invention has an organic semiconductor film containing a compound represented by Formula (1). ##STR00001##

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a patterned conductive layer and an epitaxial layer. The substrate includes a first fin structure and a second fin structure respectively protruding from a top surface of the substrate, and the second fin structure has a recess. The patterned conductive layer is disposed on the substrate and covers a first end of the first fin structure. The epitaxial layer is disposed in the recess. The first end of the first fin structure and a second end of the epitaxial layer face a first direction.

Charge transfer device having an influx portion for clock frequencies from 100 MHz
20240339529 · 2024-10-10 ·

A charge transfer device having a charge transfer channel in a semiconductor substrate. The charge transfer channel is formed by overlap of the possible electrostatic effect of the gates with the conduction layer. A clock generator has a clock frequency of more than 100 MHz which applies changes in potential at the clock frequency to the gates, for transporting charge carriers at the clock frequency from adjacent regions of the overlap between adjacent gates and the conduction layer. The charge transfer channel has an influx region which, in the flow direction, is arranged at a lateral outer boundary of the charge transfer channel and which at least partly extends over the regions of exactly two adjacent gates of the charge transfer channel in order to supply charge carriers to the charge transfer channel from a region outside the charge transfer channel that adjoins the influx region from a second charge transfer channel.

CHARGE TRANSFER DEVICE HAVING A TAPER AT THE GATE FOR CLOCK FREQUENCIES FROM 100 MHz
20240339528 · 2024-10-10 ·

A charge transfer device having a charge transfer channel in a semiconductor substrate. A doped conduction layer is provided for movably accepting the charge carriers, and a sequence of at least two electrically isolated gates which adjacently succeed one another for transferring the charge carriers in the conduction layer in a flow direction is provided. The charge transfer channel is formed by overlap of the possible electrostatic effect of the gates with the conduction layer. A clock generator has a clock frequency of more than 100 MHz which applies changes in potential at the clock frequency to the gates, for transporting charge carriers at the clock frequency from adjacent regions of the overlap between adjacent gates and the conduction layer. The charge transfer channel in the region of one gate has a region of a constriction in which the cross-section in the flow direction decreases, and has a region with a constant or widened cross-section.