Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

A thin film transistor array panel and a method of fabricating the same are described. The thin film transistor array panel has: a substrate; a gate electrode; a semiconductor layer; a source electrode; a drain electrode; an insulating layer; an etch stop layer disposed on the semiconductor layer and the insulating layer; a first electrode portion disposed on the source electrode for covering and protecting the source electrode; a second electrode portion disposed on the drain electrode for covering and protecting the drain electrode. Thus, the fabricating process can be simplified and the fabricating cost is reduced.

A thin film transistor array panel and a method of fabricating the same are described. The thin film transistor array panel has: a substrate; a gate electrode; a semiconductor layer; a source electrode; a drain electrode; an insulating layer; an etch stop layer disposed on the semiconductor layer and the insulating layer; a first electrode portion disposed on the source electrode for covering and protecting the source electrode; a second electrode portion disposed on the drain electrode for covering and protecting the drain electrode. Thus, the fabricating process can be simplified and the fabricating cost is reduced.

A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET device also includes a plurality of gate structures that partially wrap around the fin structures. The fin structures each extend in a first direction, and the gate structures each extend in a second direction different from the first direction. An epitaxial structure is formed over at least a side surface of each of the fin structures. The epitaxial structure includes: a first epi-layer, a second epi-layer, or a third epi-layer. The epitaxial structure formed over each fin structure is separated from adjacent epitaxial structures by a gap. A silicide layer is formed over each of the epitaxial structures. The silicide layer at least partially fills in the gap. Conductive contacts are formed over the silicide layer.

A semiconductor device includes a drift layer 20 of a first conductivity type, a base layer 30 of a second conductivity type that is disposed on the drift layer 20 and is connected to a source electrode 90, and a column layer 50 of a second conductivity type that is connected to the source electrode 90 and penetrates the base layer 30 to extend into the drift layer 20.

A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

The present invention provides a BOA liquid crystal panel and a manufacturing method thereof. The BOA liquid crystal panel includes a first substrate, a second substrate opposite to the first substrate, a black matrix arranged in the first substrate, a thin-film transistor arranged on the black matrix, a color resist layer arranged on the second substrate, a common electrode layer arranged on the second substrate and the color resist layer, a photoresist spacer arranged on the common electrode layer and located between the first substrate and the second substrate, and a liquid crystal layer arranged between the first substrate and the second substrate. The present invention arranges the black matrix of the liquid crystal panel in a channel that is pre-formed in a substrate to make the film thickness of the liquid crystal panel uniform and improve the display performance of the liquid crystal panel.

A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include a load transistor implemented using a buried-channel drain (BCD) structure. The load transistor may include a gate conductor, a source diffusion region, a drain diffusion region, and a buried-channel drain region that at least partially extends under the gate conductor. The BCD region may be formed before or after the formation of the gate conductor. If desired, the BCD region can also be formed at the source edge. An image sensor configured in this way can exhibit higher source-drain breakdown voltages, enhanced amplifier gain, and reduced amplifier glow.

According to one embodiment, a field-effect transistor includes a source region of a first conductivity type, a drain region of the first conductivity type and a channel region of the first conductivity type between the source region and the drain region, the source region, the drain region and the channel region being disposed in a polycrystalline semiconductor layer; a first layer including an amorphous semiconductor layer disposed on the channel region; a gate insulating layer disposed on the first layer; and a gate electrode disposed on the gate insulating layer.

A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile memory element includes a control gate electrode, a floating gate electrode, source/drain terminals, a thin first gate insulating film, and a second gate insulating film that is thick enough not to be broken down even when a voltage higher than an operating voltage of the semiconductor integrated circuit device is applied thereto, the first and second gate insulating films being formed below the control gate electrode. Thus, provided is a normally on type semiconductor nonvolatile memory element in which a threshold voltage can be regulated through injection of a large amount of charge with respect to the operating voltage from a drain terminal into the floating gate electrode via the second gate insulating film, and injected carriers do not leak in an operating voltage range.