Strain is used to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm.sup.2/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks.

Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

The present invention relates to an epitaxial structure of Ga-face group III nitride, its active device, and its gate protection device. The epitaxial structure of Ga-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-Al.sub.yGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-Al.sub.yGaN buffer layer, and an i-Al.sub.xGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage.

Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.

Gallium nitride high-electron-mobility transistors (GaN HEMTs) are at a point of rapid growth in defense (radar, SATCOM) and commercial (5G and beyond) industries. This growth also comes at a point at which the standard GaN heterostructures remain unoptimized for maximum performance. For this reason, the shift to the aluminum nitride (AlN) platform is disclosed. AlN allows for smarter, highly-scaled heterostructure design that improves the output power and thermal management of GaN amplifiers. Beyond improvements over the incumbent amplifier technology, AlN allows for a level of integration previously unachievable with GaN electronics. State-of-the-art high-current p-channel FETs, mature filter technology, and advanced waveguides, all monolithically integrated with an AlN/GaN/AlN HEMT, is made possible with aluminum nitride. It is on this AlN platform that nitride electronics may maximize their full high-power, highspeed potential for mm-wave communication and high-power logic applications.

Embodiments of this disclosure include apparatus, systems, and methods for fabricating monolayers. In one example, a method includes forming a multilayer film having a plurality of monolayers of a two-dimensional (2D) material on a growth substrate. The multilayer film has a first side proximate the growth substrate and a second side opposite the first side.

In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length l.sub.d, and 0 nm≤l.sub.d≤200 nm.