Embodiments herein include thin-film transistors (TFTs) including channel layer stacks with layers having differing mobilities. The TFTs disclosed herein transport higher total current through both the low mobility and the high mobility channel layers due to higher carrier density in high mobility channel layer and/or the high mobility channel layers, which increases the speed of response of the TFTs. The TFTs further include a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFTs are top-gate (TG), double-gate (DG), or bottom-gate (BG) TFTs. The channel layer stack includes a plurality of layers with differing mobilities. The layers with differing mobilities confer various benefits to the TFT. The high mobility layer increases the speed of response of the TFT.

A semiconductor device includes a substrate, a channel stack, source/drain contacts, and a gate electrode. The channel stack is over the substrate and includes a 2D channel layer and a barrier layer. An energy band gap of the barrier layer is greater than an energy band gap of the 2D channel layer. The source/drain contacts are in contact with the channel stack. The gate electrode is above the substrate.

A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising Al.sub.yGa.sub.1-yN on the substrate and a second layer of the first buffer layer comprising Al.sub.xGa.sub.1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising Al.sub.wGa.sub.1-wN on the first buffer layer and a second layer of the second buffer layer comprising Al.sub.zGa.sub.1-zN on the first layer of the second buffer layer, in which x>z>y>w.

A novel image processing method is provided.

In a display device in which a video signal is individually supplied to a screen divided into two, the entire screen is subjected to up-conversion processing after being divided, and another up-conversion processing is performed for a boundary portion of the screen divided into two. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion are performed in parallel with the use of a plurality of arithmetic units. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion can be performed using different algorithms.

Scalable quantum dot devices and methods are described. An example quantum dot device may comprise one or more repeated cells of a repeating quantum dot structure. The repeated cells may be arranged as a linear array of quantum dots. A single repeated cell may comprise a plurality of quantum dots. The repeated cells may be configured to cause movement of a single electron between adjacent quantum dots. A repeated cell may also comprise a charge sensor for readout of the plurality of quantum dots.

Disclosed herein are quantum dot devices with gate interface materials, as well as related computing devices and methods. For example, a quantum dot device may include a quantum well stack, a gate interface material, and a high-k gate dielectric. The gate interface material may be disposed between the high-k gate dielectric and the quantum well stack.

Disclosed herein are quantum dot devices with patterned gates, as well as related computing devices and methods. For example, a quantum dot device may include gates disposed on a quantum well stack. In some embodiments, the gates may include a first gate with a first length; two second gates with second lengths arranged such that the first gate is disposed between the second gates; and two third gates with third lengths arranged such that the second gates are disposed between the third gates; and the first, second, and third lengths may all be different. In some embodiments, the gates may include a first set of gates alternatingly arranged with a second set of gates, spacers may be disposed between gates of the first set and gates of the second set, and gates in the first or second set may include a gate dielectric having a U-shaped cross-section.

A bidirectional switch element includes: a substrate; an Al.sub.zGa.sub.1-zN layer; an Al.sub.bGa.sub.1-bN layer; a first source electrode; a first gate electrode; a second gate electrode; a second source electrode; a p-type Al.sub.x1Ga.sub.1-x1N layer; a p-type Al.sub.x2Ga.sub.1-x2N layer; an Al.sub.yGa.sub.1-yN layer; and an Al.sub.wGa.sub.1-wN layer. The Al.sub.zGa.sub.1-zN layer is formed over the substrate. The Al.sub.bGa.sub.1-bN layer is formed on the Al.sub.zGa.sub.1-zN layer. The Al.sub.yGa.sub.1-yN layer is interposed between the substrate and the Al.sub.zGa.sub.1-zN layer. The Al.sub.wGa.sub.1-wN layer is interposed between the substrate and the Al.sub.yGa.sub.1-yN layer and has a higher C concentration than the Al.sub.yGa.sub.1-yN layer.

Some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes: a substrate; a barrier layer, disposed on the substrate; a first channel layer, disposed on the barrier layer; a first gate conductor, disposed on the first channel layer; and a first doped semiconductor layer, disposed between the first gate conductor and the first channel layer, where a forbidden band width of the barrier layer is greater than a forbidden band width of the first channel layer.

A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.