A vertical field-effect transistor. The vertical field-effect transistor has: A first semiconductor layer, which has a p-type conductivity, on or over a drift region; a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure; a source-drain electrode which is electroconductively connected to the III-V-heterostructure; and a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode, and at least the region lying vertically between the contact structure and the drift region being free of the first semiconductor layer.

A core-shell nanofin vertical switch performs high-voltage switching and includes: an n-type GaN nanofin core including: an n-type drift layer; an n-type channel; and an n-type source; a p-type nanofin shell surrounding the n-type GaN nanofin core at an interface surface of the n-type GaN nanofin core, and comprising GaN; an optional source contact disposed on the n-type GaN nanofin core and the p-type nanofin shell and in electrical communication with the n-type source, such that the n-type source is interposed between the source contact and the n-type channel; and a gate contact disposed on the p-type nanofin shell and in electrical communication with the p-type nanofin shell, such that the p-type nanofin shell is interposed between the gate contact and the n-type channel, and the gate contact is interposed between the source contact and a drain contact.

Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

A nitride semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a block layer above the first nitride semiconductor layer; a first opening penetrating through the block layer; an electron transit layer and an electron supply layer provided sequentially above the block layer and along an inner surface of the first opening; a gate electrode provided above the electron supply layer to cover the first opening; a second opening penetrating through the electron supply layer and the electron transit layer; a source electrode provided in the second opening; and a drain electrode. When the first main surface is seen in a plan view, (i) the first opening and the source electrode each are elongated in a predetermined direction, and (ii) at least part of an outline of a first end of the first opening in a longitudinal direction follows an arc or an elliptical arc.

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a lattice layer, a third nitride-based semiconductor layer, a first source electrode and a second electrode, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer. The lattice layer is disposed between the first and second nitride-based semiconductor layers and doped to the first conductivity type. The lattice layer comprises a plurality of first III-V layers and second III-V layers alternatively stacked. Each of the first III-V layers has a high resistivity region and a current aperture enclosed by the high resistivity region. The high resistivity region comprises more metal oxides than the current aperture. At least two of the current apertures have different dimensions such that interfaces formed between the high resistivity regions and the current apertures misalign with each other. The gate electrode aligns with the current aperture.

The present disclosure relates to a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer. In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.

A nitride semiconductor device is provided that includes: a substrate; an n-type drift layer above the front surface of the substrate; a p-type base layer above the n-type drift layer; a gate opening in the base layer that reaches the drift layer; an n-type channel forming layer that covers the gate opening and has a channel region; a gate electrode above a section of the channel forming layer in the gate opening; an opening that is separated from the gate electrode and reaches the base layer; an opening formed in a bottom surface of said opening and reaching the drift layer; a source electrode covering the openings; and a drain electrode on the rear surface of the substrate.

An insulated gate bipolar transistor includes a P-type group III-V nitride compound layer. An N-type group III-V nitride compound layer contacts a side of the P-type group III-V nitride compound layer. An HEMT is disposed on the N-type group III-V nitride compound layer. The HEMT includes a first group III-V nitride compound layer disposed on the N-type group III-V nitride compound layer. A second group III-V nitride compound layer is disposed on the first group III-V nitride compound layer. A source is embedded within the second group III-V nitride compound layer and the first group III-V nitride compound layer, wherein the source includes an N-type group III-V nitride compound body and a metal contact. A drain contacts another side of the P-type group III-V nitride compound layer. A gate is disposed on the second group III-V nitride compound layer.

A method of forming a vertical channel transistor includes forming a first source-drain (SD) contact on a semiconductor substrate, depositing a layer of vertical channel core material on the first SD contact and depositing a layer of second SD contact material on the layer of channel core material. Also included is pattern etching the layer of second SD contact material and the layer of channel core material to form a vertical channel core having a first end connected to the first SD contact and a second end opposite to the first end and connected to a second SD contact formed by the etching the layer of second SD contact material. A vertical channel structure is formed on a sidewall of the vertical channel core, and a gate-all-around (GAA) structure is formed to completely surrounding at least a portion of the vertical channel structure.

A semiconductor device includes a substrate, a first wiring layer over the substrate, and a first array of transistor pairs extending over the first wiring layer. Cross sections of each transistor pair cut through the first array. The cross sections of each transistor pair have a similar structure. Each transistor pair includes a mandrel having two opposite sidewalls that are perpendicular to the substrate and extending along a direction of the first array of transistor pairs. Each transistor pair includes two transistors symmetrically disposed over the two opposite sidewalls of the respective mandrel.