The present application discloses a semiconductor device with an inverter and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure positioned on the substrate; a first impurity region and a second impurity region respectively positioned on two sides of the gate structure and positioned in the substrate; a first contact positioned on the first impurity region and including a first resistance; a second contact positioned on the first impurity region and including a second resistance less than the first resistance of the first contact. The first contact is configured to electrically couple to a power supply and the second contact is configured to electrically couple to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact, and the second contact together configure an inverter.

An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

The present application discloses a semiconductor device including a substrate; a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate; a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate; and wherein the first threshold voltage is different the second threshold voltage; a thickness of the first insulating stack is different from a thickness of the second insulating stack.

A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

A method for manufacturing a semiconductor structure includes: providing a substrate, at least a gate structure, a first dielectric layer covering a surface of the substrate and the gate structure being formed on the substrate, and a first dielectric layer on a side surface of the gate structure serving as a first sidewall; forming a sacrificial sidewall on a side surface of the first sidewall; removing the sacrificial sidewall after a first doped region and a second doped region are respectively formed in the substrate on both sides of the sacrificial sidewall; forming a second sidewall on a side surface of the first sidewall.

A transistor includes a vertical stack containing, in order from bottom to top or from top to bottom, a gate electrode, a gate dielectric, and an active layer and located over a substrate. The active layer includes an amorphous semiconductor material. A crystalline source region including a first portion of a crystalline semiconductor material overlies, and is electrically connected to, a first end portion of the active layer. A crystalline drain region including a second portion of the crystalline semiconductor material overlies, and is electrically connected to, a second end portion of the active layer.

In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

A semiconductor device includes a semiconductor substrate, a fin-shaped structure, a gate structure, a first doped region, a second doped region, and an intermediate region. The fin-shaped structure is disposed on and extends upwards from a top surface of the semiconductor substrate in a vertical direction. The gate structure is disposed straddling a part of the fin-shaped structure. At least a part of the first doped region is disposed in the fin-shaped structure. The second doped region is disposed in the fin-shaped structure and disposed above the first doped region in the vertical direction. The intermediate region is disposed in the fin-shaped structure. The second doped region is separated from the first doped region by the intermediate region, and a bottom surface of the gate structure is lower than or coplanar with a top surface of the first doped region in the vertical direction.

In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.