An integrated circuit, a method of forming an integrated circuit, and a semiconductor are disclosed for preventing unauthorized use in radiation-hard applications. In one embodiment, the integrated circuit comprises a silicon-on-insulator (SOI) structure, a radiation insensitive sub-circuit, and a radiation sensitive sub-circuit. The SOI structure comprises a silicon substrate, a buried oxide layer, and an active silicon layer. The radiation insensitive sub-circuit is formed on the active layer, and includes a partially depleted transistor. The radiation sensitive sub-circuit is formed on the active layer, and includes a fully depleted transistor, to prevent operation of the radiation sensitive sub-circuit under specified radiation conditions. Each of the partially depleted transistor and the fully depleted transistor includes a channel region formed in the active silicon layer, and the channel regions of the partially depleted transistor and the fully depleted transistor have substantially the same thickness but different doping concentrations.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A semiconductor component is disclosed. The semiconductor component can include: a semiconductor layer injected with a same type of dopant; a gate electrode formed above the semiconductor layer with a gate insulation film positioned in-between; a dielectric layer formed on the semiconductor layer at both sides of the gate electrode; and source/drain electrodes each formed on the dielectric layer.

A semiconductor device includes a polycrystalline silicon part buried in a termination region of a silicon layer. The polycrystalline silicon part contacts the silicon layer, has a higher crystal grain density than the silicon layer, and includes a heavy metal. The silicon layer includes a drift layer located in a cell region and the termination region. The drift layer has a lower first-conductivity-type impurity concentration than a silicon substrate. The drift layer includes a same element of heavy metal as the heavy metal included in the polycrystalline silicon part.

A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

A method of forming a semiconductor structure is provided. The method includes etching a trench in a template layer over a substrate, forming a seed structure over a bottom surface of the trench, forming a dielectric cap over the seed structure, and growing a single crystal semiconductor structure within the trench using a vapor liquid solid epitaxy growth process. The single crystal semiconductor structure is grown from a liquid-solid interface between the seed structure and the bottom surface of the trench.

An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the devices. The logic pattern is determined in accordance with processing variations during manufacture of the array. The logic pattern is represented with a first state for one or more devices with contact shorts and a second state with one or more devices without contact shorts.

A wide bandgap semiconductor device with an adjustable voltage level includes a wide bandgap semiconductor power unit and a level adjusting unit. The wide bandgap semiconductor power unit includes a source terminal, to which the level adjusting unit is electrically connected. The level adjusting unit provides a level shift voltage via the source terminal to adjust a driving voltage level of the wide bandgap semiconductor power unit. By adjusting the driving voltage level of the wide bandgap semiconductor power unit using the level adjusting unit, the wide bandgap semiconductor device may serve as a high-voltage enhancement-mode transistor to achieve reduced costs and an increased switching speed.

A stack includes a base portion consisting of silicon carbide and having a first surface that is a Si face and a carbon atom thin film disposed on the first surface and including a first main surface facing the first surface and a second main surface that is a main surface on an opposite side from the first main surface. The carbon atom thin film consists of carbon atoms. The carbon atom thin film includes at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the Si face and a graphene layer. The second main surface includes a plurality of terraces parallel to the Si face of the silicon carbide forming the base portion and a plurality of steps connecting together the plurality of terraces.

A buried channel MOSFET includes a dielectric layer, a gate and a buried channel region. The dielectric layer having a recess is disposed on a substrate. The gate is disposed in the recess, wherein the gate includes a first work function metal layer having a “-”shaped cross-sectional profile, and a minimum distance between each sidewalls of the first work function metal layer and the nearest sidewall of the recess is larger than zero. The buried channel region is located in the substrate right below the gate. The present invention provides a method of forming said buried channel MOSFET.