An embodiment of the invention shows a high-voltage MOS field-effect transistor connected in series with a Schottky diode. When the Schottky diode is forwardly biased, the high-voltage MOSFET can act as a switch and sustain a high drain-to-source voltage. When the Schottky diode is reversely biased, the Schottky diode can protect the integrate circuit where the high-voltage MOSFET is formed, because the integrate circuit might otherwise burn out due to an exceedingly-large reverse current.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

A semiconductor device may include an n type layer disposed at a first surface of an n+ type silicon carbide substrate; a p type region, a p type region, an n+ type region, and a p+ type region disposed at an upper portion in the n type layer; a gate electrode and a source electrode disposed on the n type layer and insulated from each other; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the source electrode is in contact with the p type region, the n+ type region, and the p+ type region, and the source electrode may include an ohmic junction region disposed at a contact portion of the source electrode and the n+ type region and the contact portion of the source region and the p+ type region and a Schottky junction region disposed at the contact portion of the source electrode and the p type region.

A semiconductor device may include an n type layer disposed at a first surface of an n+ type silicon carbide substrate; a trench disposed at the n type layer; a p type region, an n+ type region, and a p+ type region disposed at an upper portion in the n type layer; a gate insulating layer disposed on the n type layer, the n+ type region, and the p type region; a gate electrode disposed on the gate insulating layer; an insulating layer disposed on the gate electrode; a source electrode disposed on the insulating layer and in the trench; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the source electrode includes an ohmic junction region and a Schottky junction region.

A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.

A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

Disclosed is a graphene-based ternary barristor using a Schottky junction graphene semiconductor. A graphene channel layer is doped with N-type and N-type dopants to have two different Fermi levels and form a PN junction. Accordingly, a voltage is applied to a gate electrode layer to move the Fermi levels of the graphene channel layer and adjust the height of the Schottky barrier, thus generating current. Also, the height of the Schottky barrier is adjusted depending on the doping concentration of the graphene channel That is, the height of the Schottky barrier is changed depending on the applied gate voltage, and thus the flow of current is changed. Also, it is possible to adjust the height of the Schottky barrier by adjusting the doping concentration of the graphene channel. Accordingly, since the graphene-based ternary barristor has a high current ratio by adjusting a gate voltage, the graphene-based ternary barristor may be applied to a logic circuit.

A nonvolatile memory cell includes a first-conductivity-type silicon substrate, a metal layer formed in a surface of the first-conductivity-type silicon substrate, a second-conductivity-type diffusion layer formed in the surface of the first-conductivity-type silicon substrate and spaced apart from the metal layer, an insulating film disposed on the surface of the first-conductivity-type silicon substrate between the metal layer and the second-conductivity-type diffusion layer, a gate electrode disposed on the insulating film between the metal layer and the second-conductivity-type diffusion layer, and a sidewall disposed at a same side of the gate electrode as the metal layer and situated between the gate electrode and the metal layer, the sidewall being made of insulating material.

A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.

Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.