Disclosed is a metal-semiconductor contact structure based on two-dimensional (2D) semimetal electrodes, including a semiconductor module and a metal electrode module, where the semiconductor module is a 2D semiconductor material, and the metal electrode module is a 2D semimetal material with no dangling bonds on its surface; the 2D semiconductor material and the 2D semimetal material are interfaced with a Van der Waals interface with a surface roughness of 0.01-1 nanometer (nm) and no dangling bonds on the surface, the 2D semiconductor material and the 2D semimetal material are spaced less than 1 nm apart.

In an embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer having a first dopant concentration of boron. The device also includes and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration.

A neuromorphic devices may be formed having a three-dimensional stacked structure. The neuromorphic device may include a lower device formed on a substrate, an interlayer insulating layer formed on the substrate to cover the lower device, a synapse device having a Schottky barrier transistor structure formed on the interlayer insulating layer, and a vertical connection wiring formed in the interlayer insulating layer to electrically connect the lower device and the synapse device. The synapse device may include a channel, a source having a metal silicide forming a first Schottky junction with the channel, a drain having a metal silicide forming a second Schottky junction with the channel, a floating gate for a synaptic operation, and a control gate. The synapse device may be formed using only low-temperature processes performed at less than about 500° C.

A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion.

A method for fabricating a vertical Schottky barrier transistor includes forming fin trenches through a dielectric layer and a dummy gate stack on a substrate to expose an underlying semiconductor material. The dummy gate stack includes a bottom spacer, a dummy gate layer and a top spacer layer. Fins are epitaxially grown in the fin trenches from the underlying semiconductor material. The dummy gate layer is removed and forms a gate structure about the fins including a gate dielectric and a gate conductor. An interlevel dielectric (ILD) layer is deposited. A top of the fins is exposed to form a channel contact opening. A contact trench is formed through the ILD layer and into the underlying semiconductor material. A cavity is formed in the underlying semiconductor material below the bottom spacer layer. The cavity, the contact trench and the channel contact opening are filled with a conductive fill.

Device and method A Schottky barrier thin-film transistor (SBTFT) 200A is described. The SBTFT 200A comprises a gate contact (110), a gate insulator layer (120), a Schottky source contact (150) and a conductive oxide drain contact (140) in contact with the source contact (150). Also described is an inverter, a logic gate, an integrated circuit, an analogue circuit, a pixel for a display, for example a liquid crystal display, LCD, or an organic light emitting diode display, OLED, or a display, for example a LCD or an OLED, comprising such a Schottky barrier thin-film transistor, SBTFT. Also described is a method of providing such a Schottky barrier thin-film transistor.

A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided. A plurality of transistors are formed on the silicon including surface in at least one PMOS region and at least one NMOS region, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region. Pre-silicide cleaning removes oxide from the exposed p-type surface regions and exposed n-type surface regions. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and exposed n-type surface regions. Unreacted metal of the metal layer is stripped.

A semiconductor structure is formed with an active layer having an active device including a body region. The active device is formed by top side processing in and on a top side of a semiconductor on insulator wafer. A damaged region is formed within a portion of the body region by bottom side processing at a bottom side of the semiconductor on insulator wafer, the damaged region having a structure sufficient to prevent a kink effect and self-latching in operation of the active device.

A Schottky source-gated thin film transistor is provided including: a drain contact; an insulating substrate; a source contact made of a Schottky metal; a channel connecting the buried source contact to the drain, the channel made of ZnO; and a Schottky source barrier formed between the source contact and the channel; and a gate; wherein the source contact is positioned below the channel.

A semiconductor structure containing a vertical Schottky contact transistor is provided in which the contact resistance as well as the junction resistance is improved. The vertical Schottky contact transistor includes a bottom Schottky contact source/drain structure and a top Schottky contact source/drain structure located at opposing ends of a semiconductor channel region. The bottom Schottky contact source/drain structure includes a base portion and a vertically extending portion.