A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.

The present disclosure relates to a semiconductor device with a contact structure and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, and a dielectric layer disposed over the source/drain structure. The semiconductor device also includes a polysilicon stack disposed over the source/drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor device further includes a contact structure disposed directly over the polysilicon stack and surrounded by the dielectric layer.

A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n−1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.

A 3D NAND flash memory device includes a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion is extended axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate direct tunneling of majority carriers to the columnar channel portion to perform a program operation or an erase operation.

Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

A nitride semiconductor device 1 includes a first nitride semiconductor layer 13 that constitutes an electron transit layer, a second nitride semiconductor layer 14 that is formed on the first nitride semiconductor layer and that constitutes an electron supply layer, a semiconductor gate layer 15 that is disposed on the second nitride semiconductor layer and that has a ridge portion 15A at at-least a portion of the semiconductor gate layer and that includes an acceptor type impurity, a gate electrode 4 that is formed at least on the ridge portion of the semiconductor gate layer, a source electrode 3 and a drain electrode 5 that are disposed on the second nitride semiconductor layer, and a hole-pulling-out electrode 6 that is formed on the semiconductor gate layer in order to pull out holes existing in the semiconductor gate layer and that is electrically connected to the source electrode.

A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.