Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphisation recrystallisation then germanium condensation.

The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.

A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

A silicon carbide power device, e.g., a vertical power MOSFET or an IGBT, includes a silicon carbide wafer. A first stressor and a second stressor are arranged in the silicon carbide wafer at a first main side. A first channel region, a first portion of a drift layer and a second channel region are laterally arranged between the first stressor and the second stressor in a second lateral direction parallel to the first main side and perpendicular to the first lateral direction. A stress can be introduced by the first stressor and the second stressor in the first channel region and in the second channel region.

A field-effect transistor device and a method of isolating a field-effect transistor device. The method includes forming a layer of silicon germanium (SiGe) over a substrate, and fabricating a dummy gate stack above a silicon layer formed on the layer of SiGe. Etching the silicon layer defines a channel region below the dummy gate stack. The channel is isolated from the substrate by forming a cavity between the channel region and the substrate below the channel region, the cavity extending over a length of the channel region, wherein the length of the channel region extends from a source region to a drain region below the dummy gate stack. The cavity is filled with an oxide and a low K spacer material to isolate the channel region from the substrate.

Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.

Disclosed are a semiconductor structure and a manufacturing method therefor, solving the problem that it is difficult for an existing semiconductor structure to deplete a carrier concentration of a channel under a gate so as to achieve an enhancement-mode device. The semiconductor structure comprises: a channel layer and a barrier layer stacked in sequence. A gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region. The plurality of trenches are extended into the channel layer; and a stress applying material filled in the plurality of trenches. A lattice constant of the stress applying material is greater than that of the channel layer.

Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.