According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.

A semiconductor device with high reliability is provided. The semiconductor device includes a first insulator, a second insulator, and a transistor; the transistor includes an oxide in a channel formation region; the oxide is surrounded by the first insulator; and the first insulator is surrounded by the second insulator. The first insulator includes a region with a lower hydrogen concentration than the second insulator. Alternatively, the first insulator includes a region with a lower hydrogen concentration than the second insulator and with a lower nitrogen concentration than the second insulator.

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

An integrated circuit includes; a source region arranged in an upper portion of a substrate, a pair of split gate structures respectively on opposing sides of the source region, wherein each of the pair of split gate structures includes a floating gate electrode layer and a control gate electrode layer disposed on the floating gate electrode layer, an erase gate structure between the pair of split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures respectively on outer sidewalls of the pair of split gate structures, and a pair of gate spacers, wherein each of the gate spacers is disposed between one of the pair of split gate structures and one of the pair of selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, is further disposed on an outer side wall of the one of the pair of split gate structures, and a lowermost end of the second gate spacer is at a lower level than an upper surface of the floating gate electrode layer.

An integrated circuit includes; a source region arranged in an upper portion of a substrate, a pair of split gate structures respectively on opposing sides of the source region, wherein each of the pair of split gate structures includes a floating gate electrode layer and a control gate electrode layer disposed on the floating gate electrode layer, an erase gate structure between the pair of split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures respectively on outer sidewalls of the pair of split gate structures, and a pair of gate spacers, wherein each of the gate spacers is disposed between one of the pair of split gate structures and one of the pair of selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, is further disposed on an outer side wall of the one of the pair of split gate structures, and a lowermost end of the second gate spacer is at a lower level than an upper surface of the floating gate electrode layer.