A read-only memory cell array includes a first storage state memory cell and a second storage state memory cell. The first storage state memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage state memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.

A method for making a semi-floating gate transistor with a three-gate structure is disclosed, comprising: forming a first trench structure in isolated active regions and a first polysilicon layer, removing part of the first polysilicon layer; forming a second gate oxide layer and a second polysilicon layer; patterning isolation trench; filling an isolation dielectric layer in the isolation trench; and forming a trench between two first trench structures, to cut open the second polysilicon layer, the second gate oxide layer, the first polysilicon layer and the first gate oxide layer into two parts, so that the active region is exposed from the bottom of the trench, wherein the first polysilicon layer on either side of the trench forms a first gate, and portions of the second polysilicon layer on both sides of the isolation trench form a second gate and a third gate.

A method for making a semi-floating gate transistor with a three-gate structure is disclosed, comprising: forming a first trench structure in isolated active regions and a first polysilicon layer, removing part of the first polysilicon layer; forming a second gate oxide layer and a second polysilicon layer; patterning isolation trench; filling an isolation dielectric layer in the isolation trench; and forming a trench between two first trench structures, to cut open the second polysilicon layer, the second gate oxide layer, the first polysilicon layer and the first gate oxide layer into two parts, so that the active region is exposed from the bottom of the trench, wherein the first polysilicon layer on either side of the trench forms a first gate, and portions of the second polysilicon layer on both sides of the isolation trench form a second gate and a third gate.

A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.

The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

A multiple input device is disclosed. The multiple input device includes a semiconductor structure extending in a first direction, a first dielectric material surrounding a portion of the semiconductor structure, a floating gate on the first dielectric material and surrounding the portion of the semiconductor structure, and a second dielectric material on the floating gate and surrounding the portion of the semiconductor structure. The multiple input device also includes a plurality of control gates on the second dielectric material. At least one of the control gates extends vertically away from the semiconductor structure in a second direction and at least one of the control gates extends vertically away from the semiconductor structure in a third direction.

A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.

A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.