A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

A method for forming a pixel circuit includes forming transistors on a substrate; forming a passivation layer over the transistors; forming a contact hole to a source of a transistor; forming a transparent conductor that forms a contact in the contact hole and a resistor to control pixel current; and forming an organic light emitting diode (OLED) with an anode connecting to the resistor.

A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.

Method for producing a JFET transistor, comprising: a) producing, on a first substrate, a stack comprising a first layer comprising a first semiconductor doped according to a first conductivity type and a second layer comprising a second semiconductor doped according to a second conductivity type, the first layer being disposed between the first substrate and the second substrate, then b) securing the stack against a second substrate such that the stack is disposed between the first substrate and the second substrate, then c) removing the first substrate, then d) etching the first layer such that a remaining portion of the first layer forms a front gate of the first JFET transistor, then e) etching the second layer such that a remaining portion of the second layer is disposed below the front gate of the first JFET transistor and forms the channel, the source and the drain of the JFET transistor.

In a general aspect, a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) can include a substrate of a first conductivity type, a drift region of the first conductivity type disposed on the substrate, a spreading layer of the first conductivity type disposed in the drift region, a body region of a second conductivity type disposed in the spreading layer, and a source region of the first conductivity type disposed in the body region. The SiC MOSFET can also include a gate structure that includes a gate oxide layer, an aluminum nitride layer disposed on the gate oxide layer, and a gallium nitride layer of the second conductivity disposed on the aluminum nitride layer.

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.

A normally-closed device and a fabrication method thereof, relating to the technical field of semiconductors, is disclosed. The normally-closed device comprises a substrate, an epitaxial layer connected to the substrate comprising a first P-type nitride layer and a modified layer located on two sides of the first P-type nitride layer and formed by modifying a second P-type nitride layer in a preset region, where the first P-type nitride layer and the second P-type nitride layer are formed by epitaxially growing synchronously, a barrier layer connected to the first P-type nitride layer and the modified layer, a gate electrode connected to the barrier layer, and a source electrode and a drain electrode connected to the modified layer.

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial layers by epitaxial growth on the epitaxial silicon layer.

The present disclosure relates to the technical field of semiconductors, and provides a normally-closed device and a fabrication method thereof. The normally-closed device comprises a substrate; an epitaxial layer connected to the substrate, wherein the epitaxial layer comprises a first P-type nitride layer and a modified layer, the modified layer is located on two sides of the first P-type nitride layer, the modified layer is formed by modifying a second P-type nitride layer in a preset region, and the first P-type nitride layer and the second P-type nitride layer are formed by epitaxially growing synchronously; a barrier layer connected to the first P-type nitride layer and the modified layer; and a gate electrode connected to the barrier layer, and a source electrode and a drain electrode connected to the modified layer.