A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.

A semiconductor device, includes an insulating film formed on a substrate; a conductive layer, comprising first and second doped poly-silicon regions and a undoped poly-Si region, formed on the insulating film; a highly doped first conductivity type drain region and a highly doped a first conductivity type source region formed in the first and second doped poly-silicon regions, respectively; and a highly doped second conductivity type gate region formed in the undoped poly-Si region between the highly doped first conductivity type drain region and the highly doped first conductivity type source region. The undoped poly-Si region is disposed closer to the highly doped first conductivity type source region than the highly doped first conductivity type drain region.

A semiconductor device, includes an insulating film formed on a substrate; a conductive layer, comprising first and second doped poly-silicon regions and a undoped poly-Si region, formed on the insulating film; a highly doped first conductivity type drain region and a highly doped a first conductivity type source region formed in the first and second doped poly-silicon regions, respectively; and a highly doped second conductivity type gate region formed in the undoped poly-Si region between the highly doped first conductivity type drain region and the highly doped first conductivity type source region. The undoped poly-Si region is disposed closer to the highly doped first conductivity type source region than the highly doped first conductivity type drain region.

A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

A power SiC MOSFET with a built-in Schottky rectifier provides advantages of including a Schottky rectifier, such as avoiding bipolar degradation, while reducing a parasitic capacitive charge and related power losses, as well as system cost. A lateral built-in channel layer may enable lateral spacing of the MOSFET gate oxide from a high electric field at the Schottky contact, while also providing current limiting during short-circuit events.

Particular embodiments described herein provide for an electronic device that can include a nanowire channel. The nanowire channel can include nanowires and the nanowires can be about fifteen (15) or less angstroms apart. The nanowire channel can include more than ten (10) nanowires and can be created from a MXene material.

A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.