A silicon carbide substrate has a first main surface, and a second main surface opposite to the first main surface. A region including at least one main surface of the first and second main surfaces is made of single-crystal silicon carbide. In the one main surface, sulfur atoms are present at not less than 60×10.sup.10 atoms/cm.sup.2 and not more than 2000×10.sup.10 atoms/cm.sup.2, and carbon atoms as an impurity are present at not less than 3 at % and not more than 25 at %. Thereby, a silicon carbide substrate having a stable surface, a semiconductor device using the substrate, and methods for manufacturing them can be provided.

A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the MESFET.

A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the MESFET.

A field effect transistor according to the present invention includes a semiconductor layer including a groove, an insulating film formed on an upper surface of the semiconductor layer and having an opening above the groove and a gate electrode buried in the opening to be in contact with side surfaces and a bottom surface of the groove and having parts being in contact with an upper surface of the insulating film on both sides of the opening, wherein the gate electrode has a T-shaped sectional shape in which a width of an upper end is larger than a width of the upper surface of the insulating film.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path. A method of manufacturing such a semiconductor device is also disclosed.

A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path. A method of manufacturing such a semiconductor device is also disclosed.

Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region.

The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an Al.sub.xGa.sub.1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the Al.sub.xGa.sub.1-xN layer 12 satisfy the following equation

t≧α(a)x.sup.β(a)

Where α is expressed as Log (α)=p.sub.0+p.sub.1 log (a)+p.sub.2{log (a)}.sup.2 (p.sub.0=7.3295, p.sub.1=−3.5599, p.sub.2=0.6912) and β is expressed as β=p′.sub.0+p′.sub.1 log (a)+p′.sub.2{log (a)}.sup.2 (p′.sub.0=−3.6509, p′.sub.1=1.9445, p′.sub.2=−0.3793).

Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region.

The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an Al.sub.xGa.sub.1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the Al.sub.xGa.sub.1-xN layer 12 satisfy the following equation

t≧α(a)x.sup.β(a)

Where α is expressed as Log (α)=p.sub.0+p.sub.1 log (a)+p.sub.2{log (a)}.sup.2 (p.sub.0=7.3295, p.sub.1=−3.5599, p.sub.2=0.6912) and β is expressed as β=p′.sub.0+p′.sub.1 log (a)+p′.sub.2{log (a)}.sup.2 (p′.sub.0=−3.6509, p′.sub.1=1.9445, p′.sub.2=−0.3793).