In a multilayer substrate, a quasi-coaxial line is formed as a structure for transmitting a high-frequency signal generated by a mounted high-frequency device from an uppermost layer to a lowermost layer to externally output and for transmitting an externally input high-frequency signal from the lowermost layer to the high-frequency device. The quasi-coaxial line has: a central conductor being a vertical through hole via that connects between a metal pattern formed on an upper surface of the uppermost layer and a metal pattern formed on a lower surface of the lowermost layer; and outer conductors being a plurality of interlayer vias that are circularly arranged around the central conductor and connect between two or more layers. Whole or a part of the vertical through hole via is substituted by a capacitor structure formed of conductor pads facing each other without any via.

Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.

An electronic device may include a printed circuit board. The electronic device may include a first core with a first cavity, the first core formed from an organic material, and the first cavity configured to house a DC capacitor for delivery of direct current to a die from a voltage source. The device may include a second core with a second cavity, the second core formed from an inorganic material and the second cavity configured to house an AC capacitor coupled to an output of the die for decoupling alternating current effects associated with the direct current. The device may include an interposer layer disposed between the first core and the second core, configured to isolate the first core and the second core.

A power amplifier device includes a substrate, a power transistor die, and one or more surface mount components. The substrate has substrate die contacts exposed at a first substrate surface, and additional substrate contacts exposed at a second substrate surface. The power transistor die includes an integrated transistor. The transistor includes a control terminal and a first current conducting terminal coupled, respectively, to first and second die contacts at the first die surface, and a second current conducting terminal coupled to a third die contact at a second die surface. The surface-mount components are connected to the additional substrate components, and the surface-mount components are electrically coupled through the substrate to the first and second die contacts. The power amplifier device also includes an encapsulation material layer covering the surface-mount components and the second substrate surface.

An antenna substrate includes: a first insulating layer surrounding a cavity; a second insulating layer of which at least a portion is disposed in the cavity and containing an insulating material different from an insulating material of the first insulating layer; a first patch antenna having one surface facing the first insulating layer by an amount greater than half of an area of the first patch antenna; and a second patch antenna having one surface facing the cavity by an amount greater than half of an area of the second patch antenna.

An electronic device includes a rectangular ceramic package structure having opposite first and second sides, an interior cavity that extends to an opening in the second side, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, and non-conductive indents extending into the third and fourth sides. The device also includes a semiconductor die in the cavity, a lid that covers the opening and seals the cavity, a conductive terminal having a planar side exposed along the first side that is electrically coupled to a circuit of the semiconductor die and extends to a first one of the non-conductive indents, and conductive pins spaced apart from the conductive terminal and extending outward from the first side of the ceramic package structure along a third direction.

A signal transmission or processing assembly having a coaxial through-via within a substrate is provided. The substrate may be formed from a material that is a glass-like with an amorphous non-crystalline structure that enables the assembly to create or be created by a deep trepan or annular member that surrounds the center conductor. Methods of manufacture are employed or exploited to preserve the glass-like or other dielectric material structure of substrate to form the inner material or annular member that surrounds the center conductor or pair of center conductors.

A semiconductor package includes a redistribution substrate including a first surface and a second surface that are opposite to each other, an antenna substrate on the first surface and including a first insulating portion and antenna patterns on a top surface of the first insulating portion, and a first semiconductor chip on the second surface. The redistribution substrate includes a second insulating portion, and a redistribution pattern in the second insulating portion. The redistribution pattern includes an interconnection portion extending parallel to a top surface of the second insulating portion, and a via portion protruding from the interconnection portion toward the first surface. A width of the via portion decreases as a height in a direction from the second surface toward the first surface increases. The active surface of the first semiconductor chip is adjacent to the second surface.

A semiconductor package includes an antenna structure including an antenna member transmitting and receiving a signal through the first surface in the dielectric layer, a connection via extending from the antenna member toward the second surface, and a ground member spaced apart from the connection via, a frame surrounding the side surface of the antenna structure, a first encapsulant covering the antenna structure and the frame, a redistribution structure on the second surface and including an insulating layer in contact with the antenna structure and the frame, and a redistribution conductor electrically connected to the ground member and the connection via in the insulating layer, a first semiconductor chip on the redistribution structure and electrically connected to the antenna member through the redistribution conductor, a second encapsulant encapsulating the first semiconductor chip on the redistribution structure, and a shielding layer surrounding a surface of the second encapsulant.