Disclosed is an antenna apparatus including a radiating layer with a plurality of antenna elements forming an antenna array; a semiconductor wafer including multiple tiles each having beamforming circuits; and a multi-layer interposer. The multi-layer interposer may include: a lower dielectric layer adjacent to the substrate; an upper dielectric layer adjacent to the radiating layer; a metal layer between the lower and upper layers and including a plurality of conductive traces; a plurality of first vias extending through both the upper and lower layers and electrically coupling the beamforming circuits to the plurality of antenna elements; and a plurality of second vias extending between the beamforming circuits and the conductive traces to interconnect the tiles.

A chip comprising a bonding pad region and a transmission section. The bonding pad region has a first impedance, and is configured for electrical connection to an external transmission line. The transmission section extends away from the bonding pad region and has a second impedance. The bonding pad region is configured to enable field confinement and field matching between the bonding pad region and the external transmission line, and the second impedance is not equal to the first impedance.

The disclosed systems, structures, and methods are directed to a mm-Wave communication structure employing a first transmission structure employing a first ring transition structure followed by a first ground structure and a second ground structure configured to carry a ground signal, a second transmission structure employing a second ring transition structure followed by a third ground structure and a fourth ground structure configured to carry the ground signal, a third transmission structure configured to carry a mm-Wave signal, wherein the third transmission structure begins at the center of the first ring transition structure and the second ring transition structure and the third transmission structure is coplanar with the second transmission structure, and a fourth transmission structure configured to operatively couple an IC and the first transmission layer, the second transmission layer, and the third transmission structure.

The disclosed systems, structures, and methods are directed to a mm-Wave communication structure employing a first transmission structure employing a first ring transition structure followed by a first ground structure and a second ground structure configured to carry a ground signal, a second transmission structure employing a second ring transition structure followed by a third ground structure and a fourth ground structure configured to carry the ground signal, a third transmission structure configured to carry a mm-Wave signal, wherein the third transmission structure begins at the center of the first ring transition structure and the second ring transition structure and the third transmission structure is coplanar with the second transmission structure, and a fourth transmission structure configured to operatively couple an IC and the first transmission layer, the second transmission layer, and the third transmission structure.

A high frequency module includes: a package section including a semiconductor chip, a first portion of a backshort being integrated with the semiconductor chip by a first resin, and a first rewiring line electrically coupled to the semiconductor chip and including a portion to be an antenna coupler; and a waveguide with which a second portion of the backshort is integrated, wherein the package section and the waveguide are integrated by a second resin, to position the portion to be the antenna coupler between the waveguide and the backshort.

An electronic circuit to which the present invention is applied has a configuration in which a first substrate and a second substrate are stacked and connected to each other. The electronic circuit includes: a transmission path configured to connect a first wiring line for a signal formed in the first substrate and a second wiring for a signal formed in the second substrate to each other; and a short-circuit stub configured to connect a ground conductor provided in the first substrate and the transmission path to each other through use of three or more types of conductors.

A method of forming a semiconductor structure is provided. A first inter-level dielectric (ILD) layer is formed overlying a molding layer. The first ILD layer is patterned to form a plurality of first openings. A first lower transmitter electrode and a first lower receiver electrode are formed by depositing a first metal material within the plurality of first openings. A first dielectric waveguide is formed overlying the first ILD layer, the first lower transmitter electrode and the first lower receiver electrode. A second ILD layer is formed overlying the first dielectric waveguide and includes a plurality of second openings. A second lower transmitter electrode and a second lower receiver electrode are formed by depositing a second metal material within the plurality of second openings. A second dielectric waveguide is formed overlying the second ILD layer, the second lower transmitter electrode and the second lower receiver electrode.

Techniques regarding a scalable phased array are provided. For example, various embodiments described herein can comprise a plurality of integrated circuits having respective flip chip pads, and an antenna-in-package substrate having a ball grid array terminal and a plurality of transmission lines. The plurality of transmission lines can be embedded within the antenna-in-package substrate and can operatively couple the respective flip chip pads to the ball grid array terminal. In one or more embodiments, a die can comprise the plurality of integrated circuits. Further, in one or more embodiments a combiner can also be embedded in the antenna-in-package substrate. The combiner can join the plurality of transmission lines.

A packaging structure (100) having a split-block assembly with a first and a second conducting block section (10A,20A) and at least one transition between a first planar transmission line (2A) and a second transmission line (11A), and one or more input/output ports. The first transmission line (2A) is arranged on a substrate disposed on the first conducting block section (10A) and has a coupling section (3A), a cavity (4A) with a cavity opening in an upper surface of the first conducting block section (10A), and the second transmission line (11A) being in line with the first transmission line (2A) and located on an opposite side of the opening of the cavity (4A).

Techniques regarding a scalable phased array are provided. For example, various embodiments described herein can comprise a plurality of integrated circuits having respective flip chip pads, and an antenna-in-package substrate having a ball grid array terminal and a plurality of transmission lines. The plurality of transmission lines can be embedded within the antenna-in-package substrate and can operatively couple the respective flip chip pads to the ball grid array terminal. In one or more embodiments, a die can comprise the plurality of integrated circuits. Further, in one or more embodiments a combiner can also be embedded in the antenna-in-package substrate. The combiner can join the plurality of transmission lines.