The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprising an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and, and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer. The semiconductor device and the manufacturing method provided by the present disclosure may improve the performance of the semiconductor device.

A semiconductor apparatus including a bonding region in which a wire is bonded, includes: a semiconductor substrate; an oxide film provided on a principal surface of the semiconductor substrate in the bonding region; a polysilicon layer provided on the oxide film; an interlayer film partially provided on the polysilicon layer; a barrier metal directly provided on the polysilicon layer and the interlayer film; and an electrode provided on the barrier metal.

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

The present technology relates to a semiconductor device, a manufacturing method, and a solid-state imaging device which are capable of suppressing a decrease in bonding strength and preventing a poor electrical connection or peeling when two substrates are bonded to each other. Provided is a semiconductor device, including: a first substrate including a first electrode including a metal; and a second substrate bonded to the first substrate and including a second electrode including a metal. An acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed. The present technology can be, for example, applied to a solid-state imaging device such as a CMOS image sensor.

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.

A distribution layer structure and a manufacturing method thereof, and a bond pad structure are provided. The distribution layer structure includes a dielectric layer and a wire layer embedded in the dielectric layer. The wire layer includes a frame and a connection line, the frame has at least two openings and is divided into a plurality of segments by the at least two openings. The connection line is located in the frame and has a plurality of connecting ends connected to the frame. The connection line divides an interior of the frame into a plurality of areas, with each segment connected to one of the connecting ends, and each area connected to one of the openings. This structure provides improved binding force between the wire layer and the dielectric layer without increasing a resistance of a wire connecting with a top bond pad.

A semiconductor chip includes a substrate having a low-k material layer. An electrode pad is disposed the substrate. A first protection layer at least partially surrounds the electrode pad. The first protection layer includes a first opening at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protection layer at least partially surrounds the buffer pad. The second protection layer includes a second opening at an upper portion thereof. A pillar layer and a solder layer are sequentially stacked on the buffer pad. A thickness of the buffer pad is greater than a thickness of the electrode pad. A width of the first opening in a first direction parallel to an upper surface of the semiconductor substrate is equal to or greater than a width of the second opening in the first direction.

A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.